#define DRV_NAME "pata_pcmcia"
-#define DRV_VERSION "0.3.2"
+#define DRV_VERSION "0.3.3"
/*
* Private data structure to glue stuff together
/**
* ata_data_xfer_8bit - Transfer data by 8bit PIO
- * @adev: device to target
+ * @dev: device to target
* @buf: data buffer
* @buflen: buffer length
- * @write_data: read/write
+ * @rw: read/write
*
* Transfer data from/to the device data register by 8 bit PIO.
*
* Inherited from caller.
*/
-static void ata_data_xfer_8bit(struct ata_device *adev, unsigned char *buf,
- unsigned int buflen, int write_data)
+static unsigned int ata_data_xfer_8bit(struct ata_device *dev,
+ unsigned char *buf, unsigned int buflen, int rw)
{
- struct ata_port *ap = adev->link->ap;
- if (write_data)
- iowrite8_rep(ap->ioaddr.data_addr, buf, buflen);
- else
+ struct ata_port *ap = dev->link->ap;
+
+ if (rw == READ)
ioread8_rep(ap->ioaddr.data_addr, buf, buflen);
+ else
+ iowrite8_rep(ap->ioaddr.data_addr, buf, buflen);
+
+ return buflen;
}
/**
* pcmcia_init_one - attach a PCMCIA interface
* @pdev: pcmcia device
- * @ops: operations for this device
*
* Register a PCMCIA IDE interface. Such interfaces are PIO 0 and
* shared IRQ.
cistpl_cftable_entry_t dflt;
} *stk = NULL;
cistpl_cftable_entry_t *cfg;
- int pass, last_ret = 0, last_fn = 0, is_kme = 0, ret = -ENOMEM;
+ int pass, last_ret = 0, last_fn = 0, is_kme = 0, ret = -ENOMEM, p;
unsigned long io_base, ctl_base;
void __iomem *io_addr, *ctl_addr;
+ int n_ports = 1;
struct ata_port_operations *ops = &pcmcia_port_ops;
/* FIXME: Could be more ports at base + 0x10 but we only deal with
one right now */
if (pdev->io.NumPorts1 >= 0x20)
- printk(KERN_WARNING DRV_NAME ": second channel not yet supported.\n");
+ n_ports = 2;
if (pdev->manf_id == 0x0097 && pdev->card_id == 0x1620)
ops = &pcmcia_8bit_port_ops;
* sane.
*/
ret = -ENOMEM;
- host = ata_host_alloc(&pdev->dev, 1);
+ host = ata_host_alloc(&pdev->dev, n_ports);
if (!host)
goto failed;
- ap = host->ports[0];
- ap->ops = ops;
- ap->pio_mask = 1; /* ISA so PIO 0 cycles */
- ap->flags |= ATA_FLAG_SLAVE_POSS;
- ap->ioaddr.cmd_addr = io_addr;
- ap->ioaddr.altstatus_addr = ctl_addr;
- ap->ioaddr.ctl_addr = ctl_addr;
- ata_std_ports(&ap->ioaddr);
+ for (p = 0; p < n_ports; p++) {
+ ap = host->ports[p];
- ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io_base, ctl_base);
+ ap->ops = ops;
+ ap->pio_mask = 1; /* ISA so PIO 0 cycles */
+ ap->flags |= ATA_FLAG_SLAVE_POSS;
+ ap->ioaddr.cmd_addr = io_addr + 0x10 * p;
+ ap->ioaddr.altstatus_addr = ctl_addr + 0x10 * p;
+ ap->ioaddr.ctl_addr = ctl_addr + 0x10 * p;
+ ata_std_ports(&ap->ioaddr);
+
+ ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io_base, ctl_base);
+ }
/* activate */
ret = ata_host_activate(host, pdev->irq.AssignedIRQ, ata_interrupt,