.can_queue = ATA_DEF_QUEUE,
.this_id = ATA_SHT_THIS_ID,
.sg_tablesize = LIBATA_MAX_PRD,
- .max_sectors = ATA_MAX_SECTORS,
.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
.emulated = ATA_SHT_EMULATED,
.use_clustering = ATA_SHT_USE_CLUSTERING,
.proc_name = DRV_NAME,
.dma_boundary = ATA_DMA_BOUNDARY,
.slave_configure = ata_scsi_slave_config,
+ .slave_destroy = ata_scsi_slave_destroy,
.bios_param = ata_std_bios_param,
};
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = ata_pio_data_xfer_noirq,
.irq_handler = ata_interrupt,
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = ata_pio_data_xfer_noirq,
.irq_handler = ata_interrupt,
int pio = adev->pio_mode - XFER_PIO_0;
u8 rt;
unsigned long flags;
-
+
/* Safe as UP only. Force I/Os to occur together */
-
+
local_irq_save(flags);
-
+
/* Unlock the control interface */
do
{
while((inb(0x1F2) & 0x80) && --tries);
local_irq_restore(flags);
-
+
outb(inb(0x1F4) & 0x07, 0x1F4);
rt = inb(0x1F3);
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = pdc_data_xfer_vlb,
.irq_handler = ata_interrupt,
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = ata_pio_data_xfer, /* Check vlb/noirq */
.irq_handler = ata_interrupt,
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = ata_pio_data_xfer, /* FIXME: Check 32bit and noirq */
.irq_handler = ata_interrupt,
/*
* Opti core chipset helpers
*/
-
+
/**
* opti_syscfg - read OPTI chipset configuration
* @reg: Configuration register to read
{
unsigned long flags;
u8 r;
-
+
/* Uniprocessor chipset and must force cycles adjancent */
local_irq_save(flags);
outb(reg, 0x22);
.qc_prep = ata_qc_prep,
.qc_issue = ata_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = ata_pio_data_xfer,
.irq_handler = ata_interrupt,
.qc_prep = ata_qc_prep,
.qc_issue = opti82c46x_qc_issue_prot,
- .eng_timeout = ata_eng_timeout,
+
.data_xfer = ata_pio_data_xfer,
.irq_handler = ata_interrupt,
}
/* Probe for automatically detectable controllers */
-
+
if (io == 0x1F0 && ops == &legacy_port_ops) {
unsigned long flags;
last_port = 2;
}
- /* If an OPTI 82C46X is present find out where the channels are */
+ /* If an OPTI 82C46X is present find out where the channels are */
if (opti82c46x) {
static const char *optis[4] = {
"3/463MV", "5MV",
};
u8 chans = 1;
u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
-
+
opti82c46x = 3; /* Assume master and slave first */
printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]);
if (ctrl == 3)