* Documentation:
* Available from AMD web site.
* TODO
- * Review errata to see if serializing is neccessary
+ * Review errata to see if serializing is necessary
*/
#include <linux/kernel.h>
#include <asm/msr.h>
#define DRV_NAME "cs5535"
-#define DRV_VERSION "0.2.11"
+#define DRV_VERSION "0.2.12"
/*
* The Geode (Aka Athlon GX now) uses an internal MSR based
};
static struct ata_port_operations cs5535_port_ops = {
- .port_disable = ata_port_disable,
.set_piomode = cs5535_set_piomode,
.set_dmamode = cs5535_set_dmamode,
.mode_filter = ata_pci_default_filter,
.irq_handler = ata_interrupt,
.irq_clear = ata_bmdma_irq_clear,
.irq_on = ata_irq_on,
- .irq_ack = ata_irq_ack,
- .port_start = ata_port_start,
+ .port_start = ata_sff_port_start,
};
/**
static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
- static struct ata_port_info info = {
+ static const struct ata_port_info info = {
.sht = &cs5535_sht,
- .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
+ .flags = ATA_FLAG_SLAVE_POSS,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
- .udma_mask = 0x1f,
+ .udma_mask = ATA_UDMA4,
.port_ops = &cs5535_port_ops
};
- struct ata_port_info *ports[1] = { &info };
+ const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
u32 timings, dummy;
rdmsr(ATAC_CH0D1_PIO, timings, dummy);
if (CS5535_BAD_PIO(timings))
wrmsr(ATAC_CH0D1_PIO, 0xF7F4F7F4UL, 0);
- return ata_pci_init_one(dev, ports, 1);
+ return ata_pci_init_one(dev, ppi);
}
static const struct pci_device_id cs5535[] = {