regU &= ~(0x05 << adev->devno);
if (adev->dma_mode >= XFER_UDMA_0) {
- /* Merge thge timing value */
+ /* Merge the timing value */
regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
/* Merge the control bits */
regU |= 1 << adev->devno; /* UDMA on */