Merge branches 'release', 'cpuidle-2.6.25' and 'idle' into release

[linux-2.6] / arch / sparc64 / kernel / head.S

diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
index ac18bd8e273f5badb0df5bcd5d467f5349e50568..c4147ad8677b5307c4323ec06160b7fe541aa063 100644 (file)
--- a/arch/sparc64/kernel/head.S
+++ b/arch/sparc64/kernel/head.S
@@ -98,7 +98,7 @@ sparc64_boot:
        .globl  prom_boot_mapped_pc, prom_boot_mapping_mode
        .globl  prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
        .globl  prom_compatible_name, prom_cpu_path, prom_cpu_compatible
-       .globl  is_sun4v, sun4v_chip_type
+       .globl  is_sun4v, sun4v_chip_type, prom_set_trap_table_name
 prom_peer_name:
        .asciz  "peer"
 prom_compatible_name:
@@ -121,6 +121,8 @@ prom_map_name:
        .asciz  "map"
 prom_unmap_name:
        .asciz  "unmap"
+prom_set_trap_table_name:
+       .asciz  "SUNW,set-trap-table"
 prom_sun4v_name:
        .asciz  "sun4v"
 prom_niagara_prefix:
@@ -501,7 +503,7 @@ niagara_tlb_fixup:
        cmp     %g1, SUN4V_CHIP_NIAGARA1
        be,pt   %xcc, niagara_patch
         cmp    %g1, SUN4V_CHIP_NIAGARA2
-       be,pt   %xcc, niagara_patch
+       be,pt   %xcc, niagara2_patch
         nop
 
        call    generic_patch_copyops
@@ -512,6 +514,15 @@ niagara_tlb_fixup:
         nop
 
        ba,a,pt %xcc, 80f
+niagara2_patch:
+       call    niagara2_patch_copyops
+        nop
+       call    niagara_patch_bzero
+        nop
+       call    niagara2_patch_pageops
+        nop
+
+       ba,a,pt %xcc, 80f
 
 niagara_patch:
        call    niagara_patch_copyops
@@ -682,15 +693,38 @@ setup_trap_table:
        sethi   %hi(kern_base), %g3
        ldx     [%g3 + %lo(kern_base)], %g3
        add     %g2, %g3, %o1
+       sethi   %hi(sparc64_ttable_tl0), %o0
 
-       call    prom_set_trap_table_sun4v
-        sethi  %hi(sparc64_ttable_tl0), %o0
+       set     prom_set_trap_table_name, %g2
+       stx     %g2, [%sp + 2047 + 128 + 0x00]
+       mov     2, %g2
+       stx     %g2, [%sp + 2047 + 128 + 0x08]
+       mov     0, %g2
+       stx     %g2, [%sp + 2047 + 128 + 0x10]
+       stx     %o0, [%sp + 2047 + 128 + 0x18]
+       stx     %o1, [%sp + 2047 + 128 + 0x20]
+       sethi   %hi(p1275buf), %g2
+       or      %g2, %lo(p1275buf), %g2
+       ldx     [%g2 + 0x08], %o1
+       call    %o1
+        add    %sp, (2047 + 128), %o0
 
        ba,pt   %xcc, 2f
         nop
 
-1:     call    prom_set_trap_table
-        sethi  %hi(sparc64_ttable_tl0), %o0
+1:     sethi   %hi(sparc64_ttable_tl0), %o0
+       set     prom_set_trap_table_name, %g2
+       stx     %g2, [%sp + 2047 + 128 + 0x00]
+       mov     1, %g2
+       stx     %g2, [%sp + 2047 + 128 + 0x08]
+       mov     0, %g2
+       stx     %g2, [%sp + 2047 + 128 + 0x10]
+       stx     %o0, [%sp + 2047 + 128 + 0x18]
+       sethi   %hi(p1275buf), %g2
+       or      %g2, %lo(p1275buf), %g2
+       ldx     [%g2 + 0x08], %o1
+       call    %o1
+        add    %sp, (2047 + 128), %o0
 
        /* Start using proper page size encodings in ctx register.  */
 2:     sethi   %hi(sparc64_kern_pri_context), %g3
@@ -706,12 +740,13 @@ setup_trap_table:
 
        membar  #Sync
 
+       BRANCH_IF_SUN4V(o2, 1f)
+
        /* Kill PROM timer */
        sethi   %hi(0x80000000), %o2
        sllx    %o2, 32, %o2
        wr      %o2, 0, %tick_cmpr
 
-       BRANCH_IF_SUN4V(o2, 1f)
        BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
 
        ba,pt   %xcc, 2f