[SPARC64]: Implement rest of generic interrupt hypervisor calls.

[linux-2.6] / arch / sparc64 / kernel / entry.S

diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index b3511ff5d04a9c8ff2360f9d7e29b27261a65169..a2842a72f8e65ceadef2dba1b05c7a7ac1ba12f4 100644 (file)
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -50,7 +50,7 @@ do_fpdis:
        add             %g0, %g0, %g0
        ba,a,pt         %xcc, rtrap_clr_l6
 
-1:     TRAP_LOAD_THREAD_REG
+1:     TRAP_LOAD_THREAD_REG(%g6, %g1)
        ldub            [%g6 + TI_FPSAVED], %g5
        wr              %g0, FPRS_FEF, %fprs
        andcc           %g5, FPRS_FEF, %g0
@@ -97,10 +97,22 @@ do_fpdis:
        add             %g6, TI_FPREGS + 0x80, %g1
        faddd           %f0, %f2, %f4
        fmuld           %f0, %f2, %f6
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        add             %g6, TI_FPREGS + 0xc0, %g2
        faddd           %f0, %f2, %f8
@@ -126,11 +138,23 @@ do_fpdis:
         fzero          %f32
        mov             SECONDARY_CONTEXT, %g3
        fzero           %f34
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        add             %g6, TI_FPREGS, %g1
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        add             %g6, TI_FPREGS + 0x40, %g2
        faddd           %f32, %f34, %f36
@@ -155,10 +179,22 @@ do_fpdis:
         nop
 3:     mov             SECONDARY_CONTEXT, %g3
        add             %g6, TI_FPREGS, %g1
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        mov             0x40, %g2
        membar          #Sync
@@ -169,7 +205,13 @@ do_fpdis:
        ldda            [%g1 + %g2] ASI_BLK_S, %f48
        membar          #Sync
 fpdis_exit:
-       stxa            %g5, [%g3] ASI_DMMU
+
+661:   stxa            %g5, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g5, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
 fpdis_exit2:
        wr              %g7, 0, %gsr
@@ -190,7 +232,7 @@ fp_other_bounce:
        .globl          do_fpother_check_fitos
        .align          32
 do_fpother_check_fitos:
-       TRAP_LOAD_THREAD_REG
+       TRAP_LOAD_THREAD_REG(%g6, %g1)
        sethi           %hi(fp_other_bounce - 4), %g7
        or              %g7, %lo(fp_other_bounce - 4), %g7
 
@@ -323,10 +365,22 @@ do_fptrap_after_fsr:
        rd              %gsr, %g3
        stx             %g3, [%g6 + TI_GSR]
        mov             SECONDARY_CONTEXT, %g3
-       ldxa            [%g3] ASI_DMMU, %g5
+
+661:   ldxa            [%g3] ASI_DMMU, %g5
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       ldxa            [%g3] ASI_MMU, %g5
+       .previous
+
        sethi           %hi(sparc64_kern_sec_context), %g2
        ldx             [%g2 + %lo(sparc64_kern_sec_context)], %g2
-       stxa            %g2, [%g3] ASI_DMMU
+
+661:   stxa            %g2, [%g3] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g2, [%g3] ASI_MMU
+       .previous
+
        membar          #Sync
        add             %g6, TI_FPREGS, %g2
        andcc           %g1, FPRS_DL, %g0
@@ -341,7 +395,13 @@ do_fptrap_after_fsr:
        stda            %f48, [%g2 + %g3] ASI_BLK_S
 5:     mov             SECONDARY_CONTEXT, %g1
        membar          #Sync
-       stxa            %g5, [%g1] ASI_DMMU
+
+661:   stxa            %g5, [%g1] ASI_DMMU
+       .section        .sun4v_1insn_patch, "ax"
+       .word           661b
+       stxa            %g5, [%g1] ASI_MMU
+       .previous
+
        membar          #Sync
        ba,pt           %xcc, etrap
         wr             %g0, 0, %fprs
@@ -378,7 +438,7 @@ do_ivec:
        sllx            %g2, %g4, %g2
        sllx            %g4, 2, %g4
 
-       TRAP_LOAD_IRQ_WORK
+       TRAP_LOAD_IRQ_WORK(%g6, %g1)
 
        lduw            [%g6 + %g4], %g5        /* g5 = irq_work(cpu, pil) */
        stw             %g5, [%g3 + 0x00]       /* bucket->irq_chain = g5 */
@@ -422,7 +482,7 @@ setcc:
 
        .globl          utrap_trap
 utrap_trap:            /* %g3=handler,%g4=level */
-       TRAP_LOAD_THREAD_REG
+       TRAP_LOAD_THREAD_REG(%g6, %g1)
        ldx             [%g6 + TI_UTRAPS], %g1
        brnz,pt         %g1, invoke_utrap
         nop
@@ -1635,3 +1695,79 @@ hard_smp_processor_id:
        retl
         nop
 #endif
+
+       /* %o0: devhandle
+        * %o1: devino
+        *
+        * returns %o0: sysino
+        */
+       .globl  sun4v_devino_to_sysino
+sun4v_devino_to_sysino:
+       mov     HV_FAST_INTR_DEVINO2SYSINO, %o5
+       ta      HV_FAST_TRAP
+       retl
+        mov    %o1, %o0
+
+       /* %o0: sysino
+        *
+        * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
+        */
+       .globl  sun4v_intr_getenabled
+sun4v_intr_getenabled:
+       mov     HV_FAST_INTR_GETENABLED, %o5
+       ta      HV_FAST_TRAP
+       retl
+        mov    %o1, %o0
+
+       /* %o0: sysino
+        * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
+        */
+       .globl  sun4v_intr_setenabled
+sun4v_intr_setenabled:
+       mov     HV_FAST_INTR_SETENABLED, %o5
+       ta      HV_FAST_TRAP
+       retl
+        nop
+
+       /* %o0: sysino
+        *
+        * returns %o0: intr_state (HV_INTR_STATE_*)
+        */
+       .globl  sun4v_intr_getstate
+sun4v_intr_getstate:
+       mov     HV_FAST_INTR_GETSTATE, %o5
+       ta      HV_FAST_TRAP
+       retl
+        mov    %o1, %o0
+
+       /* %o0: sysino
+        * %o1: intr_state (HV_INTR_STATE_*)
+        */
+       .globl  sun4v_intr_setstate
+sun4v_intr_setstate:
+       mov     HV_FAST_INTR_SETSTATE, %o5
+       ta      HV_FAST_TRAP
+       retl
+        nop
+
+       /* %o0: sysino
+        *
+        * returns %o0: cpuid
+        */
+       .globl  sun4v_intr_gettarget
+sun4v_intr_gettarget:
+       mov     HV_FAST_INTR_GETTARGET, %o5
+       ta      HV_FAST_TRAP
+       retl
+        mov    %o1, %o0
+
+       /* %o0: sysino
+        * %o1: cpuid
+        */
+       .globl  sun4v_intr_settarget
+sun4v_intr_settarget:
+       mov     HV_FAST_INTR_SETTARGET, %o5
+       ta      HV_FAST_TRAP
+       retl
+        nop
+