add %g0, %g0, %g0
ba,a,pt %xcc, rtrap_clr_l6
-1: TRAP_LOAD_THREAD_REG
+1: TRAP_LOAD_THREAD_REG(%g6, %g1)
ldub [%g6 + TI_FPSAVED], %g5
wr %g0, FPRS_FEF, %fprs
andcc %g5, FPRS_FEF, %g0
add %g6, TI_FPREGS + 0x80, %g1
faddd %f0, %f2, %f4
fmuld %f0, %f2, %f6
- ldxa [%g3] ASI_DMMU, %g5
+
+661: ldxa [%g3] ASI_DMMU, %g5
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ ldxa [%g3] ASI_MMU, %g5
+ .previous
+
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
- stxa %g2, [%g3] ASI_DMMU
+
+661: stxa %g2, [%g3] ASI_DMMU
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ stxa %g2, [%g3] ASI_MMU
+ .previous
+
membar #Sync
add %g6, TI_FPREGS + 0xc0, %g2
faddd %f0, %f2, %f8
fzero %f32
mov SECONDARY_CONTEXT, %g3
fzero %f34
- ldxa [%g3] ASI_DMMU, %g5
+
+661: ldxa [%g3] ASI_DMMU, %g5
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ ldxa [%g3] ASI_MMU, %g5
+ .previous
+
add %g6, TI_FPREGS, %g1
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
- stxa %g2, [%g3] ASI_DMMU
+
+661: stxa %g2, [%g3] ASI_DMMU
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ stxa %g2, [%g3] ASI_MMU
+ .previous
+
membar #Sync
add %g6, TI_FPREGS + 0x40, %g2
faddd %f32, %f34, %f36
nop
3: mov SECONDARY_CONTEXT, %g3
add %g6, TI_FPREGS, %g1
- ldxa [%g3] ASI_DMMU, %g5
+
+661: ldxa [%g3] ASI_DMMU, %g5
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ ldxa [%g3] ASI_MMU, %g5
+ .previous
+
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
- stxa %g2, [%g3] ASI_DMMU
+
+661: stxa %g2, [%g3] ASI_DMMU
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ stxa %g2, [%g3] ASI_MMU
+ .previous
+
membar #Sync
mov 0x40, %g2
membar #Sync
ldda [%g1 + %g2] ASI_BLK_S, %f48
membar #Sync
fpdis_exit:
- stxa %g5, [%g3] ASI_DMMU
+
+661: stxa %g5, [%g3] ASI_DMMU
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ stxa %g5, [%g3] ASI_MMU
+ .previous
+
membar #Sync
fpdis_exit2:
wr %g7, 0, %gsr
.globl do_fpother_check_fitos
.align 32
do_fpother_check_fitos:
- TRAP_LOAD_THREAD_REG
+ TRAP_LOAD_THREAD_REG(%g6, %g1)
sethi %hi(fp_other_bounce - 4), %g7
or %g7, %lo(fp_other_bounce - 4), %g7
rd %gsr, %g3
stx %g3, [%g6 + TI_GSR]
mov SECONDARY_CONTEXT, %g3
- ldxa [%g3] ASI_DMMU, %g5
+
+661: ldxa [%g3] ASI_DMMU, %g5
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ ldxa [%g3] ASI_MMU, %g5
+ .previous
+
sethi %hi(sparc64_kern_sec_context), %g2
ldx [%g2 + %lo(sparc64_kern_sec_context)], %g2
- stxa %g2, [%g3] ASI_DMMU
+
+661: stxa %g2, [%g3] ASI_DMMU
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ stxa %g2, [%g3] ASI_MMU
+ .previous
+
membar #Sync
add %g6, TI_FPREGS, %g2
andcc %g1, FPRS_DL, %g0
stda %f48, [%g2 + %g3] ASI_BLK_S
5: mov SECONDARY_CONTEXT, %g1
membar #Sync
- stxa %g5, [%g1] ASI_DMMU
+
+661: stxa %g5, [%g1] ASI_DMMU
+ .section .sun4v_1insn_patch, "ax"
+ .word 661b
+ stxa %g5, [%g1] ASI_MMU
+ .previous
+
membar #Sync
ba,pt %xcc, etrap
wr %g0, 0, %fprs
sllx %g2, %g4, %g2
sllx %g4, 2, %g4
- TRAP_LOAD_IRQ_WORK
+ TRAP_LOAD_IRQ_WORK(%g6, %g1)
lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
.globl utrap_trap
utrap_trap: /* %g3=handler,%g4=level */
- TRAP_LOAD_THREAD_REG
+ TRAP_LOAD_THREAD_REG(%g6, %g1)
ldx [%g6 + TI_UTRAPS], %g1
brnz,pt %g1, invoke_utrap
nop
1: b,pt %xcc, ret_sys_call
ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
-sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
+sparc_exit: rdpr %pstate, %g2
+ wrpr %g2, PSTATE_IE, %pstate
rdpr %otherwin, %g1
rdpr %cansave, %g3
add %g3, %g1, %g3
wrpr %g3, 0x0, %cansave
wrpr %g0, 0x0, %otherwin
- wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
+ wrpr %g2, 0x0, %pstate
ba,pt %xcc, sys_exit
stb %g0, [%g6 + TI_WSAVED]
2: retl
nop
- /* Read cpu ID from hardware, return in %g6.
- * (callers_pc - 4) is in %g1. Patched at boot time.
+#ifdef CONFIG_SMP
+ .globl hard_smp_processor_id
+hard_smp_processor_id:
+ __GET_CPUID(%o0)
+ retl
+ nop
+#endif
+
+ /* %o0: devhandle
+ * %o1: devino
*
- * Default is spitfire implementation.
+ * returns %o0: sysino
+ */
+ .globl sun4v_devino_to_sysino
+sun4v_devino_to_sysino:
+ mov HV_FAST_INTR_DEVINO2SYSINO, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o1, %o0
+
+ /* %o0: sysino
*
- * The instruction sequence needs to be 5 instructions
- * in order to fit the longest implementation, which is
- * currently starfire.
+ * returns %o0: intr_enabled (HV_INTR_{DISABLED,ENABLED})
*/
- .align 32
- .globl __get_cpu_id
-__get_cpu_id:
- ldxa [%g0] ASI_UPA_CONFIG, %g6
- srlx %g6, 17, %g6
- jmpl %g1 + 0x4, %g0
- and %g6, 0x1f, %g6
- nop
+ .globl sun4v_intr_getenabled
+sun4v_intr_getenabled:
+ mov HV_FAST_INTR_GETENABLED, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o1, %o0
-__get_cpu_id_cheetah_safari:
- ldxa [%g0] ASI_SAFARI_CONFIG, %g6
- srlx %g6, 17, %g6
- jmpl %g1 + 0x4, %g0
- and %g6, 0x3ff, %g6
- nop
+ /* %o0: sysino
+ * %o1: intr_enabled (HV_INTR_{DISABLED,ENABLED})
+ */
+ .globl sun4v_intr_setenabled
+sun4v_intr_setenabled:
+ mov HV_FAST_INTR_SETENABLED, %o5
+ ta HV_FAST_TRAP
+ retl
+ nop
-__get_cpu_id_cheetah_jbus:
- ldxa [%g0] ASI_JBUS_CONFIG, %g6
- srlx %g6, 17, %g6
- jmpl %g1 + 0x4, %g0
- and %g6, 0x1f, %g6
- nop
+ /* %o0: sysino
+ *
+ * returns %o0: intr_state (HV_INTR_STATE_*)
+ */
+ .globl sun4v_intr_getstate
+sun4v_intr_getstate:
+ mov HV_FAST_INTR_GETSTATE, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o1, %o0
-__get_cpu_id_starfire:
- sethi %hi(0x1fff40000d0 >> 9), %g6
- sllx %g6, 9, %g6
- or %g6, 0xd0, %g6
- jmpl %g1 + 0x4, %g0
- lduwa [%g6] ASI_PHYS_BYPASS_EC_E, %g6
-
- .globl per_cpu_patch
-per_cpu_patch:
- sethi %hi(this_is_starfire), %o0
- lduw [%o0 + %lo(this_is_starfire)], %o1
- sethi %hi(__get_cpu_id_starfire), %o0
- brnz,pn %o1, 10f
- or %o0, %lo(__get_cpu_id_starfire), %o0
- sethi %hi(tlb_type), %o0
- lduw [%o0 + %lo(tlb_type)], %o1
- brz,pt %o1, 11f
+ /* %o0: sysino
+ * %o1: intr_state (HV_INTR_STATE_*)
+ */
+ .globl sun4v_intr_setstate
+sun4v_intr_setstate:
+ mov HV_FAST_INTR_SETSTATE, %o5
+ ta HV_FAST_TRAP
+ retl
nop
- rdpr %ver, %o0
- srlx %o0, 32, %o0
- sethi %hi(0x003e0016), %o1
- or %o1, %lo(0x003e0016), %o1
- cmp %o0, %o1
- sethi %hi(__get_cpu_id_cheetah_jbus), %o0
- be,pn %icc, 10f
- or %o0, %lo(__get_cpu_id_cheetah_jbus), %o0
- sethi %hi(__get_cpu_id_cheetah_safari), %o0
- or %o0, %lo(__get_cpu_id_cheetah_safari), %o0
-10:
- sethi %hi(__get_cpu_id), %o1
- or %o1, %lo(__get_cpu_id), %o1
- lduw [%o0 + 0x00], %o2
- stw %o2, [%o1 + 0x00]
- flush %o1 + 0x00
- lduw [%o0 + 0x04], %o2
- stw %o2, [%o1 + 0x04]
- flush %o1 + 0x04
- lduw [%o0 + 0x08], %o2
- stw %o2, [%o1 + 0x08]
- flush %o1 + 0x08
- lduw [%o0 + 0x0c], %o2
- stw %o2, [%o1 + 0x0c]
- flush %o1 + 0x0c
- lduw [%o0 + 0x10], %o2
- stw %o2, [%o1 + 0x10]
- flush %o1 + 0x10
-11:
+
+ /* %o0: sysino
+ *
+ * returns %o0: cpuid
+ */
+ .globl sun4v_intr_gettarget
+sun4v_intr_gettarget:
+ mov HV_FAST_INTR_GETTARGET, %o5
+ ta HV_FAST_TRAP
+ retl
+ mov %o1, %o0
+
+ /* %o0: sysino
+ * %o1: cpuid
+ */
+ .globl sun4v_intr_settarget
+sun4v_intr_settarget:
+ mov HV_FAST_INTR_SETTARGET, %o5
+ ta HV_FAST_TRAP
retl
nop
+
projects / linux-2.6 / blobdiff