}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
-char * __init pcibios_setup(char *str)
+char * __devinit pcibios_setup(char *str)
{
return str;
}
return result;
}
-irqreturn_t pcish5_err_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t pcish5_err_irq(int irq, void *dev_id)
{
+ struct pt_regs *regs = get_irq_regs();
unsigned pci_int, pci_air, pci_cir, pci_aint;
pci_int = SH5PCI_READ(INT);
return IRQ_HANDLED;
}
-irqreturn_t pcish5_serr_irq(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
{
printk("SERR IRQ\n");
return IRQ_NONE;
}
-#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
-
static void __init
pcibios_size_bridge(struct pci_bus *bus, struct resource *ior,
struct resource *memr)
mem_res.end -= mem_res.start;
/* Align the sizes up by bridge rules */
- io_res.end = ROUND_UP(io_res.end, 4*1024) - 1;
- mem_res.end = ROUND_UP(mem_res.end, 1*1024*1024) - 1;
+ io_res.end = ALIGN(io_res.end, 4*1024) - 1;
+ mem_res.end = ALIGN(mem_res.end, 1*1024*1024) - 1;
/* Adjust the bridge's allocation requirements */
bridge->resource[0].end = bridge->resource[0].start + io_res.end;
/* adjust parent's resource requirements */
if (ior) {
- ior->end = ROUND_UP(ior->end, 4*1024);
+ ior->end = ALIGN(ior->end, 4*1024);
ior->end += io_res.end;
}
if (memr) {
- memr->end = ROUND_UP(memr->end, 1*1024*1024);
+ memr->end = ALIGN(memr->end, 1*1024*1024);
memr->end += mem_res.end;
}
}
-#undef ROUND_UP
-
static void __init pcibios_size_bridges(void)
{
struct resource io_res, mem_res;
return -EINVAL;
}
- /* The pci subsytem needs to know where memory is and how much
+ /* The pci subsystem needs to know where memory is and how much
* of it there is. I've simply made these globals. A better mechanism
* is probably needed.
*/
subsys_initcall(pcibios_init);
-void __init pcibios_fixup_bus(struct pci_bus *bus)
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_dev *dev = bus->self;
int i;
bus->resource[0]->start = PCIBIOS_MIN_IO;
bus->resource[1]->start = PCIBIOS_MIN_MEM;
#else
- bus->resource[0]->end = 0
- bus->resource[1]->end = 0
- bus->resource[0]->start =0
- bus->resource[1]->start = 0;
+ bus->resource[0]->end = 0;
+ bus->resource[1]->end = 0;
+ bus->resource[0]->start =0;
+ bus->resource[1]->start = 0;
#endif
/* Turn off downstream PF memory address range by default */
bus->resource[2]->start = 1024*1024;