sh: intc - add a clear register to struct intc_prio_reg

[linux-2.6] / arch / sh / kernel / cpu / sh4a / setup-shx3.c

diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index f7a2cc221d22b864ef21611b67c93b3976f8442f..2c13f9ceac74ba24dcc0fb748086268264db67db 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/serial.h>
 #include <linux/io.h>
+#include <asm/mmzone.h>
 #include <asm/sci.h>
 
 static struct plat_sci_port sci_platform_data[] = {
@@ -191,18 +192,21 @@ static struct intc_mask_reg mask_registers[] = {
 };
 
 static struct intc_prio_reg prio_registers[] = {
-       { 0xfe410010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+       { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 
-       { 0xfe410800, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
-                                             TMU3, TMU2, TMU1, TMU0 } },
-       { 0xfe410804, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
-                                             SCIF3, SCIF2, SCIF1, SCIF0 } },
-       { 0xfe410808, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0, PCII56789, PCII4,
-                                             PCII3, PCII2, PCII1, PCII0 } },
-       { 0xfe41080c, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
-                                             VIN1, VIN0, IIC, DU} },
-       { 0xfe410810, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
-                                             GPIO2, GPIO1, GPIO0, IRM } },
+       { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4,
+                                                TMU3, TMU2, TMU1, TMU0 } },
+       { 0xfe410804, 0, 32, 4, /* INT2PRI1 */ { DTU3, DTU2, DTU1, DTU0,
+                                                SCIF3, SCIF2,
+                                                SCIF1, SCIF0 } },
+       { 0xfe410808, 0, 32, 4, /* INT2PRI2 */ { DMAC1, DMAC0,
+                                                PCII56789, PCII4,
+                                                PCII3, PCII2,
+                                                PCII1, PCII0 } },
+       { 0xfe41080c, 0, 32, 4, /* INT2PRI3 */ { FE1, FE0, ATAPI, VCORE0,
+                                                VIN1, VIN0, IIC, DU} },
+       { 0xfe410810, 0, 32, 4, /* INT2PRI4 */ { 0, 0, PAM, GPIO3,
+                                                GPIO2, GPIO1, GPIO0, IRM } },
 };
 
 static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities,
@@ -258,14 +262,17 @@ void __init plat_irq_setup(void)
 
 void __init plat_mem_setup(void)
 {
+       unsigned int nid = 1;
+
        /* Register CPU#0 URAM space as Node 1 */
-       setup_bootmem_node(1, 0x145f0000, 0x14610000);  /* CPU0 */
+       setup_bootmem_node(nid++, 0x145f0000, 0x14610000);      /* CPU0 */
 
 #if 0
        /* XXX: Not yet.. */
-       setup_bootmem_node(2, 0x14df0000, 0x14e10000);  /* CPU1 */
-       setup_bootmem_node(3, 0x155f0000, 0x15610000);  /* CPU2 */
-       setup_bootmem_node(4, 0x15df0000, 0x15e10000);  /* CPU3 */
-       setup_bootmem_node(5, 0x16000000, 0x16020000);  /* CSM */
+       setup_bootmem_node(nid++, 0x14df0000, 0x14e10000);      /* CPU1 */
+       setup_bootmem_node(nid++, 0x155f0000, 0x15610000);      /* CPU2 */
+       setup_bootmem_node(nid++, 0x15df0000, 0x15e10000);      /* CPU3 */
 #endif
+
+       setup_bootmem_node(nid++, 0x16000000, 0x16020000);      /* CSM */
 }