Merge branch 'linus' into x86/cleanups

[linux-2.6] / arch / sh / kernel / cpu / sh4 / probe.c

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index c478b16dbf4b1882ee75af08e5e791c854133f72..be4926969181299d26339c5dcefd84be2ae41f46 100644 (file)
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -53,7 +53,7 @@ int __init detect_cpu_and_cache_system(void)
        /*
         * Setup some generic flags we can probe on SH-4A parts
         */
-       if (((pvr >> 16) & 0xff) == 0x10) {
+       if (((pvr >> 24) & 0xff) == 0x10) {
                if ((cvr & 0x10000000) == 0)
                        boot_cpu_data.flags |= CPU_HAS_DSP;
 
@@ -132,6 +132,7 @@ int __init detect_cpu_and_cache_system(void)
 
                switch (prr) {
                case 0x50:
+               case 0x51:
                        boot_cpu_data.type = CPU_SH7723;
                        boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
                        break;
@@ -220,6 +221,12 @@ int __init detect_cpu_and_cache_system(void)
         * SH-4A's have an optional PIPT L2.
         */
        if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
+               /* Bug if we can't decode the L2 info */
+               BUG_ON(!(cvr & 0xf));
+
+               /* Silicon and specifications have clearly never met.. */
+               cvr ^= 0xf;
+
                /*
                 * Size calculation is much more sensible
                 * than it is for the L1.