sh: Encode L1/L2 cache shape in auxvt.

[linux-2.6] / arch / sh / Kconfig

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 7cfd17230224095011e57b7c1ef3692eb0fce2a3..f645f8416f1c3c6d28d7177e27ae36d41a5e7eec 100644 (file)
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -24,15 +24,12 @@ config RWSEM_GENERIC_SPINLOCK
        bool
        default y
 
-config SUPERH64
-       def_bool y if CPU_SH5
-
 config RWSEM_XCHGADD_ALGORITHM
        bool
 
 config GENERIC_BUG
        def_bool y
-       depends on BUG
+       depends on BUG && SUPERH32
 
 config GENERIC_FIND_NEXT_BIT
        bool
@@ -161,10 +158,20 @@ config CPU_SUBTYPE_SH7619
 
 # SH-2A Processor Support
 
+config CPU_SUBTYPE_SH7203
+       bool "Support SH7203 processor"
+       select CPU_SH2A
+       select CPU_HAS_FPU
+
 config CPU_SUBTYPE_SH7206
        bool "Support SH7206 processor"
        select CPU_SH2A
 
+config CPU_SUBTYPE_SH7263
+       bool "Support SH7263 processor"
+       select CPU_SH2A
+       select CPU_HAS_FPU
+
 # SH-3 Processor Support
 
 config CPU_SUBTYPE_SH7705
@@ -508,17 +515,10 @@ config SH_MAGIC_PANEL_R2
        help
          Select Magic Panel R2 if configuring for Magic Panel R2.
 
-config SH_SIMULATOR
-       bool "Simulator"
-       depends on SUPERH64
-
 config SH_CAYMAN
        bool "Hitachi Cayman"
        depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103
-
-config SH_HARP
-       bool "ST50 Harp"
-       depends on CPU_SH5
+       select SYS_SUPPORTS_PCI
 
 endmenu
 
@@ -566,7 +566,8 @@ config SH_PCLK_FREQ
        default "32000000" if CPU_SUBTYPE_SH7722
        default "33333333" if CPU_SUBTYPE_SH7770 || \
                              CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
-                             CPU_SUBTYPE_SH7206
+                             CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
+                             CPU_SUBTYPE_SH7263
        default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
        default "66000000" if CPU_SUBTYPE_SH4_202
        default "50000000"
@@ -577,7 +578,7 @@ config SH_PCLK_FREQ
 
 config SH_CLK_MD
        int "CPU Mode Pin Setting"
-       depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206
+       depends on CPU_SH2
        default 6 if CPU_SUBTYPE_SH7206
        default 5 if CPU_SUBTYPE_SH7619
        default 0
@@ -691,7 +692,7 @@ source "kernel/Kconfig.preempt"
 
 config GUSA
        def_bool y
-       depends on !SMP
+       depends on !SMP && SUPERH32
        help
          This enables support for gUSA (general UserSpace Atomicity).
          This is the default implementation for both UP and non-ll/sc
@@ -703,6 +704,16 @@ config GUSA
          This should only be disabled for special cases where alternate
          atomicity implementations exist.
 
+config GUSA_RB
+       bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)"
+       depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A)
+       help
+         Enabling this option will allow the kernel to implement some
+         atomic operations using a software implemention of load-locked/
+         store-conditional (LLSC). On machines which do not have hardware
+         LLSC, this should be more efficient than the other alternative of
+         disabling insterrupts around the atomic sequence.
+
 endmenu
 
 menu "Boot options"