};
static irqreturn_t
-pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+pq2pci_irq_demux(int irq, void *dev_id)
{
unsigned long stat, mask, pend;
int bit;
break;
for (bit = 0; pend != 0; ++bit, pend <<= 1) {
if (pend & 0x80000000)
- __do_IRQ(NR_CPM_INTS + bit, regs);
+ __do_IRQ(NR_CPM_INTS + bit);
}
}
static struct irqaction pq2pci_irqaction = {
.handler = pq2pci_irq_demux,
- .flags = SA_INTERRUPT,
+ .flags = IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "PQ2 PCI cascade",
};
{
int irq;
volatile cpm2_map_t *immap = cpm2_immr;
-#if defined CONFIG_ADS8272
- /* configure chip select for PCI interrupt controller */
- immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
- immap->im_memctl.memc_or3 = 0xffff8010;
-#elif defined CONFIG_PQ2FADS
- immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
- immap->im_memctl.memc_or8 = 0xffff8010;
-#endif
for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
irq_desc[irq].chip = &pq2pci_ic;
CPM high 0b0000
CPM middle 0b0001
CPM low 0b0010
- PCI reguest 0b0011
+ PCI request 0b0011
Reserved 0b0100
Reserved 0b0101
Internal Core 0b0110
immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
#endif
-#if defined CONFIG_ADS8272
- immap->im_siu_conf.siu_82xx.sc_siumcr =
- (immap->im_siu_conf.siu_82xx.sc_siumcr &
- ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
- SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
- SIUMCR_LBPC11 | SIUMCR_APPC11 |
- SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
- SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
- SIUMCR_APPC10 | SIUMCR_CS10PC00 |
- SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
-
-#elif defined CONFIG_PQ2FADS
- /*
- * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
- * and local bus for PCI (SIUMCR [LBPC]).
- */
- immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
- ~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
- SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10);
-#endif
/* Enable PCI */
immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
-#if defined CONFIG_ADS8272
- /* PCI int highest prio */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
-#elif defined CONFIG_PQ2FADS
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
-#endif
/* park bus on PCI */
immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
hose->bus_offset = 0;
hose->last_busno = 0xff;
-#ifdef CONFIG_ADS8272
- hose->set_cfg_type = 1;
-#endif
-
setup_m8260_indirect_pci(hose,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_data);