-
/*
- * arch/ppc/platforms/hdpu_setup.c
- *
* Board setup routines for the Sky Computers HDPU Compute Blade.
*
* Written by Brian Waite <waite@skycomputers.com>
* option) any later version.
*/
-#include <linux/config.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/irq.h>
-#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
/* Enable pipelining */
mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
- /* Enable Snoop Pipelineing */
+ /* Enable Snoop Pipelining */
mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
/*
}
#endif
-static int __init hdpu_platform_notify(struct device *dev)
+static int hdpu_platform_notify(struct device *dev)
{
static struct {
char *bus_id;
}
}
-#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
-static void
-hdpu_ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
-{
- request_region(from, extent, name);
- return;
-}
-
-static void hdpu_ide_release_region(ide_ioreg_t from, unsigned int extent)
-{
- release_region(from, extent);
- return;
-}
-
-static void __init
-hdpu_ide_pci_init_hwif_ports(hw_regs_t * hw, ide_ioreg_t data_port,
- ide_ioreg_t ctrl_port, int *irq)
-{
- struct pci_dev *dev;
-
- pci_for_each_dev(dev) {
- if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) ||
- ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)) {
- hw->irq = dev->irq;
-
- if (irq != NULL) {
- *irq = dev->irq;
- }
- }
- }
-
- return;
-}
-#endif
-
void hdpu_heartbeat(void)
{
if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
char hdpu_smp0[] = "SMP Cpu #0";
char hdpu_smp1[] = "SMP Cpu #1";
-static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id,
- struct pt_regs *regs)
+static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id)
{
volatile unsigned int doorbell;
mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
if (doorbell & 1) {
- smp_message_recv(0, regs);
+ smp_message_recv(0);
}
if (doorbell & 2) {
- smp_message_recv(1, regs);
+ smp_message_recv(1);
}
if (doorbell & 4) {
- smp_message_recv(2, regs);
+ smp_message_recv(2);
}
if (doorbell & 8) {
- smp_message_recv(3, regs);
+ smp_message_recv(3);
}
return IRQ_HANDLED;
}
-static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id,
- struct pt_regs *regs)
+static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id)
{
volatile unsigned int doorbell;
mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
if (doorbell & 1) {
- smp_message_recv(0, regs);
+ smp_message_recv(0);
}
if (doorbell & 2) {
- smp_message_recv(1, regs);
+ smp_message_recv(1);
}
if (doorbell & 4) {
- smp_message_recv(2, regs);
+ smp_message_recv(2);
}
if (doorbell & 8) {
- smp_message_recv(3, regs);
+ smp_message_recv(3);
}
return IRQ_HANDLED;
}
mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
request_irq(60, hdpu_smp_cpu0_int_handler,
- SA_INTERRUPT, hdpu_smp0, 0);
+ IRQF_DISABLED, hdpu_smp0, 0);
}
if (cpu_nr == 1) {
mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
request_irq(28, hdpu_smp_cpu1_int_handler,
- SA_INTERRUPT, hdpu_smp1, 0);
+ IRQF_DISABLED, hdpu_smp1, 0);
}
}