Merge master.kernel.org:/pub/scm/linux/kernel/git/paulus/powerpc

[linux-2.6] / arch / powerpc / sysdev / cpm2_common.c

diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c
index f7a04892400b3f266fd9ab55173f7d2c85eb072d..ec265995d5d8bc020837c766f35ac3ed6de25ad3 100644 (file)
--- a/arch/powerpc/sysdev/cpm2_common.c
+++ b/arch/powerpc/sysdev/cpm2_common.c
@@ -51,6 +51,7 @@ cpm_cpm2_t    *cpmp;          /* Pointer to comm processor space */
  * the communication processor devices.
  */
 cpm2_map_t *cpm2_immr;
+intctl_cpm2_t *cpm2_intctl;
 
 #define CPM_MAP_SIZE   (0x40000)       /* 256k - the PQ3 reserve this amount
                                           of space for CPM as it is larger
@@ -60,6 +61,7 @@ void
 cpm2_reset(void)
 {
        cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
+       cpm2_intctl = cpm2_map(im_intctl);
 
        /* Reclaim the DP memory for our use.
         */
@@ -94,13 +96,15 @@ cpm_setbrg(uint brg, uint rate)
        /* This is good enough to get SMCs running.....
        */
        if (brg < 4) {
-               bp = (uint *)&cpm2_immr->im_brgc1;
+               bp = cpm2_map_size(im_brgc1, 16);
        } else {
-               bp = (uint *)&cpm2_immr->im_brgc5;
+               bp = cpm2_map_size(im_brgc5, 16);
                brg -= 4;
        }
        bp += brg;
        *bp = ((BRG_UART_CLK / rate) << 1) | CPM_BRG_EN;
+
+       cpm2_unmap(bp);
 }
 
 /* This function is used to set high speed synchronous baud rate
@@ -112,16 +116,108 @@ cpm2_fastbrg(uint brg, uint rate, int div16)
        volatile uint   *bp;
 
        if (brg < 4) {
-               bp = (uint *)&cpm2_immr->im_brgc1;
+               bp = cpm2_map_size(im_brgc1, 16);
        }
        else {
-               bp = (uint *)&cpm2_immr->im_brgc5;
+               bp = cpm2_map_size(im_brgc5, 16);
                brg -= 4;
        }
        bp += brg;
        *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
        if (div16)
                *bp |= CPM_BRG_DIV16;
+
+       cpm2_unmap(bp);
+}
+
+int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
+{
+       int ret = 0;
+       int shift;
+       int i, bits = 0;
+       cpmux_t *im_cpmux;
+       u32 *reg;
+       u32 mask = 7;
+       u8 clk_map [24][3] = {
+               {CPM_CLK_FCC1, CPM_BRG5, 0},
+               {CPM_CLK_FCC1, CPM_BRG6, 1},
+               {CPM_CLK_FCC1, CPM_BRG7, 2},
+               {CPM_CLK_FCC1, CPM_BRG8, 3},
+               {CPM_CLK_FCC1, CPM_CLK9, 4},
+               {CPM_CLK_FCC1, CPM_CLK10, 5},
+               {CPM_CLK_FCC1, CPM_CLK11, 6},
+               {CPM_CLK_FCC1, CPM_CLK12, 7},
+               {CPM_CLK_FCC2, CPM_BRG5, 0},
+               {CPM_CLK_FCC2, CPM_BRG6, 1},
+               {CPM_CLK_FCC2, CPM_BRG7, 2},
+               {CPM_CLK_FCC2, CPM_BRG8, 3},
+               {CPM_CLK_FCC2, CPM_CLK13, 4},
+               {CPM_CLK_FCC2, CPM_CLK14, 5},
+               {CPM_CLK_FCC2, CPM_CLK15, 6},
+               {CPM_CLK_FCC2, CPM_CLK16, 7},
+               {CPM_CLK_FCC3, CPM_BRG5, 0},
+               {CPM_CLK_FCC3, CPM_BRG6, 1},
+               {CPM_CLK_FCC3, CPM_BRG7, 2},
+               {CPM_CLK_FCC3, CPM_BRG8, 3},
+               {CPM_CLK_FCC3, CPM_CLK13, 4},
+               {CPM_CLK_FCC3, CPM_CLK14, 5},
+               {CPM_CLK_FCC3, CPM_CLK15, 6},
+               {CPM_CLK_FCC3, CPM_CLK16, 7}
+               };
+
+       im_cpmux = cpm2_map(im_cpmux);
+
+       switch (target) {
+       case CPM_CLK_SCC1:
+               reg = &im_cpmux->cmx_scr;
+               shift = 24;
+       case CPM_CLK_SCC2:
+               reg = &im_cpmux->cmx_scr;
+               shift = 16;
+               break;
+       case CPM_CLK_SCC3:
+               reg = &im_cpmux->cmx_scr;
+               shift = 8;
+               break;
+       case CPM_CLK_SCC4:
+               reg = &im_cpmux->cmx_scr;
+               shift = 0;
+               break;
+       case CPM_CLK_FCC1:
+               reg = &im_cpmux->cmx_fcr;
+               shift = 24;
+               break;
+       case CPM_CLK_FCC2:
+               reg = &im_cpmux->cmx_fcr;
+               shift = 16;
+               break;
+       case CPM_CLK_FCC3:
+               reg = &im_cpmux->cmx_fcr;
+               shift = 8;
+               break;
+       default:
+               printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
+               return -EINVAL;
+       }
+
+       if (mode == CPM_CLK_RX)
+               shift +=3;
+
+       for (i=0; i<24; i++) {
+               if (clk_map[i][0] == target && clk_map[i][1] == clock) {
+                       bits = clk_map[i][2];
+                       break;
+               }
+       }
+       if (i == sizeof(clk_map)/3)
+           ret = -EINVAL;
+
+       bits <<= shift;
+       mask <<= shift;
+       out_be32(reg, (in_be32(reg) & ~mask) | bits);
+
+       cpm2_unmap(im_cpmux);
+       return ret;
 }
 
 /*
@@ -132,11 +228,14 @@ static spinlock_t cpm_dpmem_lock;
  * until the memory subsystem goes up... */
 static rh_block_t cpm_boot_dpmem_rh_block[16];
 static rh_info_t cpm_dpmem_info;
+static u8* im_dprambase;
 
 static void cpm2_dpinit(void)
 {
        spin_lock_init(&cpm_dpmem_lock);
 
+       im_dprambase = ioremap(CPM_MAP_ADDR, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
+
        /* initialize the info header */
        rh_init(&cpm_dpmem_info, 1,
                        sizeof(cpm_boot_dpmem_rh_block) /
@@ -205,6 +304,6 @@ EXPORT_SYMBOL(cpm_dpdump);
 
 void *cpm_dpram_addr(uint offset)
 {
-       return (void *)&cpm2_immr->im_dprambase[offset];
+       return (void *)(im_dprambase + offset);
 }
 EXPORT_SYMBOL(cpm_dpram_addr);