Merge branch 'for-2.6.26' of master.kernel.org:/pub/scm/linux/kernel/git/jwboyer...

[linux-2.6] / arch / powerpc / platforms / cell / spufs / backing_ops.c

diff --git a/arch/powerpc/platforms/cell/spufs/backing_ops.c b/arch/powerpc/platforms/cell/spufs/backing_ops.c
index 15f915813710f22a3ab347b84d39a4b2d65cdb4d..64eb15b22040aec7f005b0d70f264318f7b650a7 100644 (file)
--- a/arch/powerpc/platforms/cell/spufs/backing_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/backing_ops.c
@@ -106,16 +106,20 @@ static unsigned int spu_backing_mbox_stat_poll(struct spu_context *ctx,
                if (stat & 0xff0000)
                        ret |= POLLIN | POLLRDNORM;
                else {
-                       ctx->csa.priv1.int_stat_class0_RW &= ~0x1;
-                       ctx->csa.priv1.int_mask_class2_RW |= 0x1;
+                       ctx->csa.priv1.int_stat_class2_RW &=
+                               ~CLASS2_MAILBOX_INTR;
+                       ctx->csa.priv1.int_mask_class2_RW |=
+                               CLASS2_ENABLE_MAILBOX_INTR;
                }
        }
        if (events & (POLLOUT | POLLWRNORM)) {
                if (stat & 0x00ff00)
                        ret = POLLOUT | POLLWRNORM;
                else {
-                       ctx->csa.priv1.int_stat_class0_RW &= ~0x10;
-                       ctx->csa.priv1.int_mask_class2_RW |= 0x10;
+                       ctx->csa.priv1.int_stat_class2_RW &=
+                               ~CLASS2_MAILBOX_THRESHOLD_INTR;
+                       ctx->csa.priv1.int_mask_class2_RW |=
+                               CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR;
                }
        }
        spin_unlock_irq(&ctx->csa.register_lock);
@@ -139,7 +143,7 @@ static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data)
                ret = 4;
        } else {
                /* make sure we get woken up by the interrupt */
-               ctx->csa.priv1.int_mask_class2_RW |= 0x1UL;
+               ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
                ret = 0;
        }
        spin_unlock(&ctx->csa.register_lock);
@@ -169,7 +173,8 @@ static int spu_backing_wbox_write(struct spu_context *ctx, u32 data)
        } else {
                /* make sure we get woken up by the interrupt when space
                   becomes available */
-               ctx->csa.priv1.int_mask_class2_RW |= 0x10;
+               ctx->csa.priv1.int_mask_class2_RW |=
+                       CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR;
                ret = 0;
        }
        spin_unlock(&ctx->csa.register_lock);
@@ -283,6 +288,12 @@ static void spu_backing_runcntl_write(struct spu_context *ctx, u32 val)
        spin_lock(&ctx->csa.register_lock);
        ctx->csa.prob.spu_runcntl_RW = val;
        if (val & SPU_RUNCNTL_RUNNABLE) {
+               ctx->csa.prob.spu_status_R &=
+                       ~SPU_STATUS_STOPPED_BY_STOP &
+                       ~SPU_STATUS_STOPPED_BY_HALT &
+                       ~SPU_STATUS_SINGLE_STEP &
+                       ~SPU_STATUS_INVALID_INSTR &
+                       ~SPU_STATUS_INVALID_CH;
                ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
        } else {
                ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
@@ -368,7 +379,7 @@ static int spu_backing_send_mfc_command(struct spu_context *ctx,
 
 static void spu_backing_restart_dma(struct spu_context *ctx)
 {
-       /* nothing to do here */
+       ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
 }
 
 struct spu_context_ops spu_backing_ops = {