#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
-#include <asm/ibm4xx.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
*
* This is all going to change RSN when we add bi_recs....... -- Dan
*/
- .text
-_GLOBAL(_stext)
-_GLOBAL(_start)
+ .section .text.head, "ax"
+_ENTRY(_stext);
+_ENTRY(_start);
/* Save parameters we are passed.
*/
*/
. = 0xc0
crit_save:
-_GLOBAL(crit_r10)
+_ENTRY(crit_r10)
.space 4
-_GLOBAL(crit_r11)
+_ENTRY(crit_r11)
.space 4
/*
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- lis r11, TASK_SIZE@h
+ lis r11, PAGE_OFFSET@h
cmplw r10, r11
blt+ 3f
lis r11, swapper_pg_dir@h
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- lis r11, TASK_SIZE@h
+ lis r11, PAGE_OFFSET@h
cmplw r10, r11
blt+ 3f
lis r11, swapper_pg_dir@h
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- lis r11, TASK_SIZE@h
+ lis r11, PAGE_OFFSET@h
cmplw r10, r11
blt+ 3f
lis r11, swapper_pg_dir@h
*/
lwz r9, tlb_4xx_index@l(0)
addi r9, r9, 1
- andi. r9, r9, (PPC4XX_TLB_SIZE-1)
+ andi. r9, r9, (PPC40X_TLB_SIZE-1)
stw r9, tlb_4xx_index@l(0)
6:
* The PowerPC 4xx family of processors do not have an FPU, so this just
* returns.
*/
-_GLOBAL(giveup_fpu)
+_ENTRY(giveup_fpu)
blr
/* This is where the main kernel code starts.
.space 4096
.globl swapper_pg_dir
swapper_pg_dir:
- .space 4096
+ .space PGD_TABLE_SIZE
/* Stack for handling critical exceptions from kernel mode */
.globl exception_stack_top
exception_stack_top:
-/* This space gets a copy of optional info passed to us by the bootstrap
- * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
- */
- .globl cmd_line
-cmd_line:
- .space 512
-
/* Room for two PTE pointers, usually the kernel and current user pointers
* to their respective root page table.
*/