* cycles after the IT fires. But it's arbitrary how much time passes
* before we call it "late". I've picked one second.
*/
- if (ticks_elapsed > HZ) {
+ if (unlikely(ticks_elapsed > HZ)) {
/* Scenario 3: very long delay? bad in any case */
printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!"
" cycles %lX rem %lX "
write_sequnlock(&xtime_lock);
}
- /* check soft power switch status */
- if (cpu == 0 && !atomic_read(&power_tasklet.count))
- tasklet_schedule(&power_tasklet);
-
return IRQ_HANDLED;
}
.mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
.mult = 0, /* to be set */
.shift = 22,
- .is_continuous = 1,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
+#ifdef CONFIG_SMP
+int update_cr16_clocksource(void)
+{
+ /* since the cr16 cycle counters are not synchronized across CPUs,
+ we'll check if we should switch to a safe clocksource: */
+ if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) {
+ clocksource_change_rating(&clocksource_cr16, 0);
+ return 1;
+ }
-/*
- * XXX: We can do better than this.
- * Returns nanoseconds
- */
-
-unsigned long long sched_clock(void)
+ return 0;
+}
+#else
+int update_cr16_clocksource(void)
{
- return (unsigned long long)jiffies * (1000000000 / HZ);
+ return 0; /* no change */
}
-
+#endif /*CONFIG_SMP*/
void __init start_cpu_itimer(void)
{
current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */
clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz,
clocksource_cr16.shift);
- /* lower the rating if we already know its unstable: */
- if (num_online_cpus()>1)
- clocksource_cr16.rating = 200;
-
clocksource_register(&clocksource_cr16);
if (pdc_tod_read(&tod_data) == 0) {