#define vpe_id() smp_processor_id()
#else
#define WHAT 0
-#define vpe_id() smp_processor_id()
+#define vpe_id() 0
#endif
#define __define_perf_accessors(r, n, np) \
__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
-__define_perf_accessors(perfcntr, 2, 2)
-__define_perf_accessors(perfcntr, 3, 2)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
-__define_perf_accessors(perfctrl, 2, 2)
-__define_perf_accessors(perfctrl, 3, 2)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
struct op_mips_model op_model_mipsxx_ops;
int i;
/* Compute the performance counter control word. */
- /* For now count kernel and user mode */
for (i = 0; i < counters; i++) {
reg.control[i] = 0;
reg.counter[i] = 0;
unsigned int counters = op_model_mipsxx_ops.num_counters;
unsigned int control;
unsigned int counter;
- int handled = 0;
+ int handled = IRQ_NONE;
+
+ if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+ return handled;
switch (counters) {
#define HANDLE_COUNTER(n) \
(counter & M_COUNTER_OVERFLOW)) { \
oprofile_add_sample(get_irq_regs(), n); \
w_c0_perfcntr ## n(reg.counter[n]); \
- handled = 1; \
+ handled = IRQ_HANDLED; \
}
HANDLE_COUNTER(3)
HANDLE_COUNTER(2)
counters = __n_counters();
}
-#ifdef CONFIG_MIPS_MT_SMP
- counters >> 1;
-#endif
return counters;
}
reset_counters(counters);
+#ifdef CONFIG_MIPS_MT_SMP
+ counters >>= 1;
+#endif
+
op_model_mipsxx_ops.num_counters = counters;
switch (current_cpu_data.cputype) {
case CPU_20KC:
static void mipsxx_exit(void)
{
- reset_counters(op_model_mipsxx_ops.num_counters);
+ int counters = op_model_mipsxx_ops.num_counters;
+#ifdef CONFIG_MIPS_MT_SMP
+ counters <<= 1;
+#endif
+ reset_counters(counters);
perf_irq = null_perf_irq;
}