.unmask = bf561_internal_unmask_irq,
};
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned int bf561_gpio_irq_startup(unsigned int irq)
{
unsigned int ret;
+ char buf[8];
u16 gpionr = irq - IRQ_PF0;
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
{
unsigned int ret;
+ char buf[8];
u16 gpionr = irq - IRQ_PF0;
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-
- ret = gpio_request(gpionr, "IRQ");
+ snprintf(buf, sizeof buf, "IRQ %d", irq);
+ ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
-#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
-
void __init init_exception_vectors(void)
{
SSYNC();
set_irq_chip(irq, &bf561_core_irqchip);
else
set_irq_chip(irq, &bf561_internal_irqchip);
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+
if ((irq != IRQ_PROG0_INTA) &&
- (irq != IRQ_PROG1_INTA) && (irq != IRQ_PROG2_INTA)) {
-#endif
+ (irq != IRQ_PROG1_INTA) &&
+ (irq != IRQ_PROG2_INTA))
set_irq_handler(irq, handle_simple_irq);
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
- } else {
+ else
set_irq_chained_handler(irq, bf561_demux_gpio_irq);
- }
-#endif
-
}
-#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
set_irq_chip(irq, &bf561_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq);
}
-#endif
+
bfin_write_IMASK(0);
CSYNC();
ilat = bfin_read_ILAT();
}
#ifdef CONFIG_DO_IRQ_L1
-void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text));
+__attribute__((l1_text))
#endif
-
void do_irq(int vec, struct pt_regs *fp)
{
if (vec == EVT_IVTMR_P) {