Merge branch 'release' of git://lm-sensors.org/kernel/mhoffman/hwmon-2.6

[linux-2.6] / arch / blackfin / mach-bf537 / head.S

diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 3014fe8dd1556bf717421422873e1f7ead28ab04..6b019eaee0b61e7847043ebee2503bae4493900f 100644 (file)
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -32,14 +32,11 @@
 #include <asm/blackfin.h>
 #include <asm/trace.h>
 
-#if CONFIG_BFIN_KERNEL_CLOCK
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
 #include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
 
-.global __rambase
-.global __ramstart
-.global __ramend
 .extern ___bss_stop
 .extern ___bss_start
 .extern _bf53x_relocate_l1_mem
@@ -180,40 +177,28 @@ ENTRY(__start)
        SSYNC;
 #endif
 
-#ifdef CONFIG_BF537_PORT_H
-       p0.h = hi(PORTH_FER);
-       p0.l = lo(PORTH_FER);
-       R0.L = W[P0]; /* Read */
-       SSYNC;
-       R0 = 0x0000;
-       W[P0] = R0.L; /* Write */
-       SSYNC;
-       W[P0] = R0.L; /* Disable peripheral function of PORTH */
-       SSYNC;
-#endif
-
        /* Initialise UART - when booting from u-boot, the UART is not disabled
         * so if we dont initalize here, our serial console gets hosed */
-       p0.h = hi(UART_LCR);
-       p0.l = lo(UART_LCR);
+       p0.h = hi(BFIN_UART_LCR);
+       p0.l = lo(BFIN_UART_LCR);
        r0 = 0x0(Z);
        w[p0] = r0.L;   /* To enable DLL writes */
        ssync;
 
-       p0.h = hi(UART_DLL);
-       p0.l = lo(UART_DLL);
+       p0.h = hi(BFIN_UART_DLL);
+       p0.l = lo(BFIN_UART_DLL);
        r0 = 0x0(Z);
        w[p0] = r0.L;
        ssync;
 
-       p0.h = hi(UART_DLH);
-       p0.l = lo(UART_DLH);
+       p0.h = hi(BFIN_UART_DLH);
+       p0.l = lo(BFIN_UART_DLH);
        r0 = 0x00(Z);
        w[p0] = r0.L;
        ssync;
 
-       p0.h = hi(UART_GCTL);
-       p0.l = lo(UART_GCTL);
+       p0.h = hi(BFIN_UART_GCTL);
+       p0.l = lo(BFIN_UART_GCTL);
        r0 = 0x0(Z);
        w[p0] = r0.L;   /* To enable UART clock */
        ssync;
@@ -232,7 +217,7 @@ ENTRY(__start)
 
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
-#if CONFIG_BFIN_KERNEL_CLOCK
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
        call _start_dma_code;
 #endif
 
@@ -365,7 +350,7 @@ ENDPROC(_real_start)
 __FINIT
 
 .section .l1.text
-#if CONFIG_BFIN_KERNEL_CLOCK
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
 ENTRY(_start_dma_code)
 
        /* Enable PHY CLK buffer output */
@@ -445,12 +430,6 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
 
-       p0.l = LO(EBIU_SDBCTL);
-       p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
-       r0 = mem_SDBCTL;
-       w[p0] = r0.l;
-       ssync;
-
        P2.H = hi(EBIU_SDGCTL);
        P2.L = lo(EBIU_SDGCTL);
        R0 = [P2];
@@ -483,18 +462,3 @@ ENTRY(_start_dma_code)
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-.data
-
-/*
- * Set up the usable of RAM stuff. Size of RAM is determined then
- * an initial stack set up at the end.
- */
-
-.align 4
-__rambase:
-.long   0
-__ramstart:
-.long   0
-__ramend:
-.long   0