[SOCK]: Adds a rcu_dereference() in sk_filter

[linux-2.6] / arch / blackfin / mach-bf537 / head.S

diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 82ea047059174fd8401b2d9910b47c368a12b585..3014fe8dd1556bf717421422873e1f7ead28ab04 100644 (file)
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -51,10 +51,12 @@ __INIT
 ENTRY(__start)
        /* R0: argument of command line string, passed from uboot, save it */
        R7 = R0;
-       /* Set the SYSCFG register:
-        * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
-        */
-       R0 = 0x36;
+       /* Enable Cycle Counter and Nesting Of Interrupts */
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
+       R0 = SYSCFG_SNEN;
+#else
+       R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
        SYSCFG = R0;
        R0 = 0;
 
@@ -96,7 +98,7 @@ ENTRY(__start)
        M2 = r0;
        M3 = r0;
 
-       trace_buffer_start(p0,r0);
+       trace_buffer_init(p0,r0);
        P0 = R1;
        R0 = R1;
 
@@ -222,6 +224,12 @@ ENTRY(__start)
        fp = sp;
        usp = sp;
 
+#ifdef CONFIG_EARLY_PRINTK
+       SP += -12;
+       call _init_early_exception_vectors;
+       SP += 12;
+#endif
+
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
 #if CONFIG_BFIN_KERNEL_CLOCK
@@ -476,85 +484,6 @@ ENTRY(_start_dma_code)
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
 
-ENTRY(_bfin_reset)
-       /* No more interrupts to be handled*/
-       CLI R6;
-       SSYNC;
-
-#if defined(CONFIG_MTD_M25P80)
-       /*
-        * The following code fix the SPI flash reboot issue,
-        * /CS signal of the chip which is using PF10 return to GPIO mode
-        */
-       p0.h = hi(PORTF_FER);
-       p0.l = lo(PORTF_FER);
-       r0.l = 0x0000;
-       w[p0] = r0.l;
-       SSYNC;
-
-       /* /CS return to high */
-       p0.h = hi(PORTFIO);
-       p0.l = lo(PORTFIO);
-       r0.l = 0xFFFF;
-       w[p0] = r0.l;
-       SSYNC;
-
-       /* Delay some time, This is necessary */
-       r1.h = 0;
-       r1.l = 0x400;
-       p1   = r1;
-       lsetup (.L_delay_lab1, .L_delay_lab1_end) lc1 = p1;
-.L_delay_lab1:
-       r0.h = 0;
-       r0.l = 0x8000;
-       p0   = r0;
-       lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
-.L_delay_lab0:
-       nop;
-.L_delay_lab0_end:
-       nop;
-.L_delay_lab1_end:
-       nop;
-#endif
-
-       /* Clear the IMASK register */
-       p0.h = hi(IMASK);
-       p0.l = lo(IMASK);
-       r0 = 0x0;
-       [p0] = r0;
-
-       /* Clear the ILAT register */
-       p0.h = hi(ILAT);
-       p0.l = lo(ILAT);
-       r0 = [p0];
-       [p0] = r0;
-       SSYNC;
-
-       /* make sure SYSCR is set to use BMODE */
-       P0.h = hi(SYSCR);
-       P0.l = lo(SYSCR);
-       R0.l = 0x0;
-       W[P0] = R0.l;
-       SSYNC;
-
-       /* issue a system soft reset */
-       P1.h = hi(SWRST);
-       P1.l = lo(SWRST);
-       R1.l = 0x0007;
-       W[P1] = R1;
-       SSYNC;
-
-       /* clear system soft reset */
-       R0.l = 0x0000;
-       W[P0] = R0;
-       SSYNC;
-
-       /* issue core reset */
-       raise 1;
-
-       RTS;
-ENDPROC(_bfin_reset)
-
 .data
 
 /*