Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/teigland/dlm

[linux-2.6] / arch / blackfin / mach-bf533 / head.S

diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 1ded945a6fa0212973a122b24d022bd79751cd2c..c671e8549b17fd5d95da3fa5117f7fb476c70f7e 100644 (file)
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -31,14 +31,11 @@
 #include <linux/init.h>
 #include <asm/blackfin.h>
 #include <asm/trace.h>
-#if CONFIG_BFIN_KERNEL_CLOCK
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
 #include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
 
-.global __rambase
-.global __ramstart
-.global __ramend
 .extern ___bss_stop
 .extern ___bss_start
 .extern _bf53x_relocate_l1_mem
@@ -151,26 +148,26 @@ ENTRY(__start)
 
        /* Initialise UART - when booting from u-boot, the UART is not disabled
         * so if we dont initalize here, our serial console gets hosed */
-       p0.h = hi(UART_LCR);
-       p0.l = lo(UART_LCR);
+       p0.h = hi(BFIN_UART_LCR);
+       p0.l = lo(BFIN_UART_LCR);
        r0 = 0x0(Z);
        w[p0] = r0.L;   /* To enable DLL writes */
        ssync;
 
-       p0.h = hi(UART_DLL);
-       p0.l = lo(UART_DLL);
+       p0.h = hi(BFIN_UART_DLL);
+       p0.l = lo(BFIN_UART_DLL);
        r0 = 0x0(Z);
        w[p0] = r0.L;
        ssync;
 
-       p0.h = hi(UART_DLH);
-       p0.l = lo(UART_DLH);
+       p0.h = hi(BFIN_UART_DLH);
+       p0.l = lo(BFIN_UART_DLH);
        r0 = 0x00(Z);
        w[p0] = r0.L;
        ssync;
 
-       p0.h = hi(UART_GCTL);
-       p0.l = lo(UART_GCTL);
+       p0.h = hi(BFIN_UART_GCTL);
+       p0.l = lo(BFIN_UART_GCTL);
        r0 = 0x0(Z);
        w[p0] = r0.L;   /* To enable UART clock */
        ssync;
@@ -189,7 +186,7 @@ ENTRY(__start)
 
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
-#if CONFIG_BFIN_KERNEL_CLOCK
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
        call _start_dma_code;
 #endif
 
@@ -322,7 +319,7 @@ ENDPROC(_real_start)
 __FINIT
 
 .section .l1.text
-#if CONFIG_BFIN_KERNEL_CLOCK
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
 ENTRY(_start_dma_code)
        p0.h = hi(SIC_IWR);
        p0.l = lo(SIC_IWR);
@@ -393,12 +390,6 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
 
-       p0.l = LO(EBIU_SDBCTL);
-       p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
-       r0 = mem_SDBCTL;
-       w[p0] = r0.l;
-       ssync;
-
        P2.H = hi(EBIU_SDGCTL);
        P2.L = lo(EBIU_SDGCTL);
        R0 = [P2];
@@ -431,18 +422,3 @@ ENTRY(_start_dma_code)
        RTS;
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
-
-.data
-
-/*
- * Set up the usable of RAM stuff. Size of RAM is determined then
- * an initial stack set up at the end.
- */
-
-.align 4
-__rambase:
-.long   0
-__ramstart:
-.long   0
-__ramend:
-.long   0