[PACKET]: Fix sparse warnings in af_packet.c

[linux-2.6] / arch / arm / plat-s3c24xx / sleep.S

diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 2018c2e1dcc5aecc97a9c9ec1825fc3c6b2fc29c..a646cbe8244cfdd73add087b1b68f91bb831e85a 100644 (file)
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -1,4 +1,4 @@
-/* linux/arch/arm/mach-s3c2410/sleep.S
+/* linux/arch/arm/plat-s3c24xx/sleep.S
  *
  * Copyright (c) 2004 Simtec Electronics
  *     Ben Dooks <ben@simtec.co.uk>
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
  * reset the UART configuration, only enable if you really need this!
@@ -64,11 +64,10 @@ ENTRY(s3c2410_cpu_save)
 
        @@ store co-processor registers
 
-       mrc     p15, 0, r4, c15, c1, 0  @ CP access register
-       mrc     p15, 0, r5, c13, c0, 0  @ PID
-       mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
-       mrc     p15, 0, r7, c2, c0, 0   @ translation table base address
-       mrc     p15, 0, r8, c1, c0, 0   @ control register
+       mrc     p15, 0, r4, c13, c0, 0  @ PID
+       mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+       mrc     p15, 0, r6, c2, c0, 0   @ translation table base address
+       mrc     p15, 0, r7, c1, c0, 0   @ control register
 
        stmia   r0, { r4 - r13 }
 
@@ -97,6 +96,14 @@ resume_with_mmu:
 s3c2410_sleep_save_phys:
        .word   0
 
+
+       /* sleep magic, to allow the bootloader to check for an valid
+        * image to resume to. Must be the first word before the
+        * s3c2410_cpu_resume entry.
+       */
+
+       .word   0x2bedf00d
+
        /* s3c2410_cpu_resume
         *
         * resume code entry for bootloader to call
@@ -141,10 +148,9 @@ ENTRY(s3c2410_cpu_resume)
        ldr     r0, s3c2410_sleep_save_phys     @ address of restore block
        ldmia   r0, { r4 - r13 }
 
-       mcr     p15, 0, r4, c15, c1, 0          @ CP access register
-       mcr     p15, 0, r5, c13, c0, 0          @ PID
-       mcr     p15, 0, r6, c3, c0, 0           @ Domain ID
-       mcr     p15, 0, r7, c2, c0, 0           @ translation table base
+       mcr     p15, 0, r4, c13, c0, 0          @ PID
+       mcr     p15, 0, r5, c3, c0, 0           @ Domain ID
+       mcr     p15, 0, r6, c2, c0, 0           @ translation table base
 
 #ifdef CONFIG_DEBUG_RESUME
        mov     r3, #'R'
@@ -152,7 +158,7 @@ ENTRY(s3c2410_cpu_resume)
 #endif
 
        ldr     r2, =resume_with_mmu
-       mcr     p15, 0, r8, c1, c0, 0           @ turn on MMU, etc
+       mcr     p15, 0, r7, c1, c0, 0           @ turn on MMU, etc
        nop                                     @ second-to-last before mmu
        mov     pc, r2                          @ go back to virtual address