#include <linux/init.h>
#include <linux/module.h>
#include <linux/irq.h>
+#include <linux/sysdev.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
#include "generic.h"
#endif
};
-void __init pxa_init_gpio(int gpio_nr)
-{
- int i;
-
- /* add a GPIO chip for each register bank.
- * the last PXA25x register only contains 21 GPIOs
- */
- for (i = 0; i < gpio_nr; i += 32) {
- if (i+32 > gpio_nr)
- pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i;
- gpiochip_add(&pxa_gpio_chip[i/32].chip);
- }
-}
-
/*
* PXA GPIO edge detection for IRQs:
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
* Use this instead of directly setting GRER/GFER.
*/
-static long GPIO_IRQ_rising_edge[4];
-static long GPIO_IRQ_falling_edge[4];
-static long GPIO_IRQ_mask[4];
+static unsigned long GPIO_IRQ_rising_edge[4];
+static unsigned long GPIO_IRQ_falling_edge[4];
+static unsigned long GPIO_IRQ_mask[4];
+
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static int __gpio_is_occupied(unsigned gpio)
+{
+ if (cpu_is_pxa25x() || cpu_is_pxa27x())
+ return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
+ else
+ return 0;
+}
static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
{
GPIO_IRQ_falling_edge[idx] |
GPDR(gpio)) & GPIO_bit(gpio))
return 0;
- if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
+
+ if (__gpio_is_occupied(gpio))
return 0;
+
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
- pxa_gpio_mode(gpio | GPIO_IN);
+ GPDR(gpio) &= ~GPIO_bit(gpio);
if (type & IRQ_TYPE_EDGE_RISING)
__set_bit(gpio, GPIO_IRQ_rising_edge);
.set_type = pxa_gpio_irq_type,
};
-void __init pxa_init_irq_gpio(int gpio_nr)
+void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
{
- int irq, i;
+ int irq, i, gpio;
pxa_last_gpio = gpio_nr - 1;
/* Install handler for GPIO>=2 edge detect interrupts */
set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
- pxa_init_gpio(gpio_nr);
+ pxa_low_gpio_chip.set_wake = fn;
+ pxa_muxed_gpio_chip.set_wake = fn;
+
+ /* add a GPIO chip for each register bank.
+ * the last PXA25x register only contains 21 GPIOs
+ */
+ for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
+ if (gpio + 32 > gpio_nr)
+ pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
+ gpiochip_add(&pxa_gpio_chip[i].chip);
+ }
+}
+
+#ifdef CONFIG_PM
+
+static unsigned long saved_gplr[4];
+static unsigned long saved_gpdr[4];
+static unsigned long saved_grer[4];
+static unsigned long saved_gfer[4];
+
+static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+ int i, gpio;
+
+ for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+ saved_gplr[i] = GPLR(gpio);
+ saved_gpdr[i] = GPDR(gpio);
+ saved_grer[i] = GRER(gpio);
+ saved_gfer[i] = GFER(gpio);
+
+ /* Clear GPIO transition detect bits */
+ GEDR(gpio) = GEDR(gpio);
+ }
+ return 0;
}
-void __init pxa_init_gpio_set_wake(int (*set_wake)(unsigned int, unsigned int))
+static int pxa_gpio_resume(struct sys_device *dev)
{
- pxa_low_gpio_chip.set_wake = set_wake;
- pxa_muxed_gpio_chip.set_wake = set_wake;
+ int i, gpio;
+
+ for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+ /* restore level with set/clear */
+ GPSR(gpio) = saved_gplr[i];
+ GPCR(gpio) = ~saved_gplr[i];
+
+ GRER(gpio) = saved_grer[i];
+ GFER(gpio) = saved_gfer[i];
+ GPDR(gpio) = saved_gpdr[i];
+ }
+ return 0;
+}
+#else
+#define pxa_gpio_suspend NULL
+#define pxa_gpio_resume NULL
+#endif
+
+struct sysdev_class pxa_gpio_sysclass = {
+ .name = "gpio",
+ .suspend = pxa_gpio_suspend,
+ .resume = pxa_gpio_resume,
+};
+
+static int __init pxa_gpio_init(void)
+{
+ return sysdev_class_register(&pxa_gpio_sysclass);
}
+
+core_initcall(pxa_gpio_init);