#include <linux/spinlock.h>
#include <asm/io.h>
+#include <asm/mach-types.h>
#include <asm/arch/gpmc.h>
#undef DEBUG
static struct resource gpmc_mem_root;
static struct resource gpmc_cs_mem[GPMC_CS_NUM];
-static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED;
+static DEFINE_SPINLOCK(gpmc_mem_lock);
static unsigned gpmc_cs_map;
static void __iomem *gpmc_base =
}
/* TODO: Add support for gpmc_fck to clock framework and use it */
-static unsigned long gpmc_get_fclk_period(void)
+unsigned long gpmc_get_fclk_period(void)
{
/* In picoseconds */
return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
else
ticks = gpmc_ns_to_ticks(time);
nr_bits = end_bit - st_bit + 1;
- if (ticks >= 1 << nr_bits)
+ if (ticks >= 1 << nr_bits) {
+#ifdef DEBUG
+ printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
+ cs, name, time, ticks, 1 << nr_bits);
+#endif
return -1;
+ }
mask = (1 << nr_bits) - 1;
l = gpmc_cs_read_reg(cs, reg);
#ifdef DEBUG
- printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n",
+ printk(KERN_INFO
+ "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
- (l >> st_bit) & mask);
+ (l >> st_bit) & mask, time);
#endif
l &= ~(mask << st_bit);
l |= ticks << st_bit;
div = l / gpmc_get_fclk_period();
if (div > 4)
return -1;
- if (div < 0)
+ if (div <= 0)
div = 1;
return div;
GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
+ /* caller is expected to have initialized CONFIG1 to cover
+ * at least sync vs async
+ */
+ l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+ if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
#ifdef DEBUG
- printk(KERN_INFO "GPMC CS%d CLK period is %lu (div %d)\n",
- cs, gpmc_get_fclk_period(), div);
+ printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
+ cs, (div * gpmc_get_fclk_period()) / 1000, div);
#endif
-
- l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
- l &= ~0x03;
- l |= (div - 1);
+ l &= ~0x03;
+ l |= (div - 1);
+ gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
+ }
return 0;
}
return l & (1 << 6);
}
-static void gpmc_cs_set_reserved(int cs, int reserved)
+int gpmc_cs_set_reserved(int cs, int reserved)
{
+ if (cs > GPMC_CS_NUM)
+ return -ENODEV;
+
gpmc_cs_map &= ~(1 << cs);
gpmc_cs_map |= (reserved ? 1 : 0) << cs;
+
+ return 0;
}
-static int gpmc_cs_reserved(int cs)
+int gpmc_cs_reserved(int cs)
{
+ if (cs > GPMC_CS_NUM)
+ return -ENODEV;
+
return gpmc_cs_map & (1 << cs);
}
int cs;
unsigned long boot_rom_space = 0;
- if (cpu_is_omap242x()) {
- u32 l;
- l = omap_readl(OMAP242X_CONTROL_STATUS);
- /* In case of internal boot the 1st MB is redirected to the
- * boot ROM memory space.
- */
- if (l & (1 << 3))
- boot_rom_space = BOOT_ROM_SPACE;
- } else
- /* We assume internal boot if the mode can't be
- * determined.
- */
- boot_rom_space = BOOT_ROM_SPACE;
+ /* never allocate the first page, to facilitate bug detection;
+ * even if we didn't boot from ROM.
+ */
+ boot_rom_space = BOOT_ROM_SPACE;
+ /* In apollon the CS0 is mapped as 0x0000 0000 */
+ if (machine_is_omap_apollon())
+ boot_rom_space = 0;
gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
gpmc_mem_root.end = GPMC_MEM_END;