/*
- * arch/arm/mach-ixp2000/common.c
+ * arch/arm/mach-ixp2000/core.c
*
* Common routines used by all IXP2400/2800 based platforms.
*
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware.h>
-#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/tlbflush.h>
*************************************************************************/
void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
{
-
spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
- ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
+ ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
}
void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
- ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
+ ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
spin_unlock_irqrestore(&ixp2000_slowport_lock,
ixp2000_slowport_irq_flags);
static struct map_desc ixp2000_io_desc[] __initdata = {
{
.virtual = IXP2000_CAP_VIRT_BASE,
- .physical = IXP2000_CAP_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
.length = IXP2000_CAP_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_INTCTL_VIRT_BASE,
- .physical = IXP2000_INTCTL_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
.length = IXP2000_INTCTL_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_PCI_CREG_VIRT_BASE,
- .physical = IXP2000_PCI_CREG_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
.length = IXP2000_PCI_CREG_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_PCI_CSR_VIRT_BASE,
- .physical = IXP2000_PCI_CSR_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
.length = IXP2000_PCI_CSR_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_MSF_VIRT_BASE,
- .physical = IXP2000_MSF_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
.length = IXP2000_MSF_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_PCI_IO_VIRT_BASE,
- .physical = IXP2000_PCI_IO_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
.length = IXP2000_PCI_IO_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
- .physical = IXP2000_PCI_CFG0_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
.length = IXP2000_PCI_CFG0_SIZE,
.type = MT_DEVICE
}, {
.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
- .physical = IXP2000_PCI_CFG1_PHYS_BASE,
+ .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
.length = IXP2000_PCI_CFG1_SIZE,
.type = MT_DEVICE
}
iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
/* Set slowport to 8-bit mode. */
- ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
+ ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
}
static struct resource ixp2000_uart_resource = {
.start = IXP2000_UART_PHYS_BASE,
- .end = IXP2000_UART_PHYS_BASE + 0xffff,
+ .end = IXP2000_UART_PHYS_BASE + 0x1f,
.flags = IORESOURCE_MEM,
};
write_seqlock(&xtime_lock);
/* clear timer 1 */
- ixp2000_reg_write(IXP2000_T1_CLR, 1);
+ ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
timer_tick(regs);
ixp2000_reg_write(IXP2000_T4_CLR, 0);
ixp2000_reg_write(IXP2000_T4_CLD, -1);
- ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
+ ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
missing_jiffy_timer_csr = IXP2000_T4_CSR;
} else {
ixp2000_reg_write(IXP2000_T2_CLR, 0);
ixp2000_reg_write(IXP2000_T2_CLD, -1);
- ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
+ ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
missing_jiffy_timer_csr = IXP2000_T2_CSR;
}
next_jiffy_time = 0xffffffff;
ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
- ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
+ ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
}
void gpio_line_config(int line, int direction)
GPIO_IRQ_level_high &= ~(1 << line);
update_gpio_int_csrs();
- ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line);
+ ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
} else if (direction == GPIO_IN) {
- ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
+ ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
}
local_irq_restore(flags);
}
ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
- ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
+ ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
}
static void ixp2000_GPIO_irq_mask(unsigned int irq)
{
- ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
+ ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
}
static void ixp2000_GPIO_irq_unmask(unsigned int irq)
{
unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
if (irq == IRQ_IXP2000_PCIA)
- ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
+ ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
else if (irq == IRQ_IXP2000_PCIB)
- ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
+ ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
}
static void ixp2000_pci_irq_unmask(unsigned int irq)
static void ixp2000_irq_mask(unsigned int irq)
{
- ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
+ ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
}
static void ixp2000_irq_unmask(unsigned int irq)
ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
/* clear PCI interrupt sources */
- ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
+ ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
/*
* Certain bits in the IRQ status register of the