+#ifndef __MIPSEL__
+/*
+ * ASIC PCI registers for big endian configuration.
+ */
+#define PCIMT_UCONF 0xbfff0004
+#define PCIMT_IOADTIMEOUT2 0xbfff000c
+#define PCIMT_IOMEMCONF 0xbfff0014
+#define PCIMT_IOMMU 0xbfff001c
+#define PCIMT_IOADTIMEOUT1 0xbfff0024
+#define PCIMT_DMAACCESS 0xbfff002c
+#define PCIMT_DMAHIT 0xbfff0034
+#define PCIMT_ERRSTATUS 0xbfff003c
+#define PCIMT_ERRADDR 0xbfff0044
+#define PCIMT_SYNDROME 0xbfff004c
+#define PCIMT_ITPEND 0xbfff0054
+#define IT_INT2 0x01
+#define IT_INTD 0x02
+#define IT_INTC 0x04
+#define IT_INTB 0x08
+#define IT_INTA 0x10
+#define IT_EISA 0x20
+#define IT_SCSI 0x40
+#define IT_ETH 0x80
+#define PCIMT_IRQSEL 0xbfff005c
+#define PCIMT_TESTMEM 0xbfff0064
+#define PCIMT_ECCREG 0xbfff006c
+#define PCIMT_CONFIG_ADDRESS 0xbfff0074
+#define PCIMT_ASIC_ID 0xbfff007c /* read */
+#define PCIMT_SOFT_RESET 0xbfff007c /* write */
+#define PCIMT_PIA_OE 0xbfff0084
+#define PCIMT_PIA_DATAOUT 0xbfff008c
+#define PCIMT_PIA_DATAIN 0xbfff0094
+#define PCIMT_CACHECONF 0xbfff009c
+#define PCIMT_INVSPACE 0xbfff00a4
+#else