+/*******************************************************************************
+ *
+ * FADT - Fixed ACPI Description Table (Signature "FACP")
+ *
+ ******************************************************************************/
+
+/* Fields common to all versions of the FADT */
+
+struct acpi_table_fadt {
+ struct acpi_table_header header; /* Common ACPI table header */
+ u32 facs; /* 32-bit physical address of FACS */
+ u32 dsdt; /* 32-bit physical address of DSDT */
+ u8 model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
+ u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */
+ u16 sci_interrupt; /* System vector of SCI interrupt */
+ u32 smi_command; /* 32-bit Port address of SMI command port */
+ u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
+ u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
+ u8 S4bios_request; /* Value to write to SMI CMD to enter S4BIOS state */
+ u8 pstate_control; /* Processor performance state control */
+ u32 pm1a_event_block; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */
+ u32 pm1b_event_block; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */
+ u32 pm1a_control_block; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */
+ u32 pm1b_control_block; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */
+ u32 pm2_control_block; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */
+ u32 pm_timer_block; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */
+ u32 gpe0_block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */
+ u32 gpe1_block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */
+ u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */
+ u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */
+ u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */
+ u8 pm_timer_length; /* Byte Length of ports at pm_timer_block */
+ u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */
+ u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */
+ u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */
+ u8 cst_control; /* Support for the _CST object and C States change notification */
+ u16 C2latency; /* Worst case HW latency to enter/exit C2 state */
+ u16 C3latency; /* Worst case HW latency to enter/exit C3 state */
+ u16 flush_size; /* Processor's memory cache line width, in bytes */
+ u16 flush_stride; /* Number of flush strides that need to be read */
+ u8 duty_offset; /* Processor duty cycle index in processor's P_CNT reg */
+ u8 duty_width; /* Processor duty cycle value bit width in P_CNT register. */
+ u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */
+ u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */
+ u8 century; /* Index to century in RTC CMOS RAM */
+ u16 boot_flags; /* IA-PC Boot Architecture Flags. See Table 5-10 for description */