+/*
+ * Calculate internal data-transfer-clock cycle from input-clock
+ * frequency (/MHz) and fill 'sx_table'.
+ *
+ * The original driver used to rely on a fixed sx_table, containing periods
+ * for (only) the lower limits of the respective input-clock-frequency ranges
+ * (8-10/12-15/16-20 MHz). Although it seems, that no problems ocurred with
+ * this setting so far, it might be desirable to adjust the transfer periods
+ * closer to the really attached, possibly 25% higher, input-clock, since
+ * - the wd33c93 may really use a significant shorter period, than it has
+ * negotiated (eg. thrashing the target, which expects 4/8MHz, with 5/10MHz
+ * instead).
+ * - the wd33c93 may ask the target for a lower transfer rate, than the target
+ * is capable of (eg. negotiating for an assumed minimum of 252ns instead of
+ * possible 200ns, which indeed shows up in tests as an approx. 10% lower
+ * transfer rate).
+ */
+static inline unsigned int
+round_4(unsigned int x)
+{
+ switch (x & 3) {
+ case 1: --x;
+ break;
+ case 2: ++x;
+ case 3: ++x;
+ }
+ return x;
+}
+
+static void
+calc_sx_table(unsigned int mhz, struct sx_period sx_table[9])
+{
+ unsigned int d, i;
+ if (mhz < 11)
+ d = 2; /* divisor for 8-10 MHz input-clock */
+ else if (mhz < 16)
+ d = 3; /* divisor for 12-15 MHz input-clock */
+ else
+ d = 4; /* divisor for 16-20 MHz input-clock */
+
+ d = (100000 * d) / 2 / mhz; /* 100 x DTCC / nanosec */
+
+ sx_table[0].period_ns = 1;
+ sx_table[0].reg_value = 0x20;
+ for (i = 1; i < 8; i++) {
+ sx_table[i].period_ns = round_4((i+1)*d / 100);
+ sx_table[i].reg_value = (i+1)*0x10;
+ }
+ sx_table[7].reg_value = 0;
+ sx_table[8].period_ns = 0;
+ sx_table[8].reg_value = 0;
+}
+
+/*
+ * check and, maybe, map an init- or "clock:"- argument.
+ */
+static uchar
+set_clk_freq(int freq, int *mhz)
+{
+ int x = freq;
+ if (WD33C93_FS_8_10 == freq)
+ freq = 8;
+ else if (WD33C93_FS_12_15 == freq)
+ freq = 12;
+ else if (WD33C93_FS_16_20 == freq)
+ freq = 16;
+ else if (freq > 7 && freq < 11)
+ x = WD33C93_FS_8_10;
+ else if (freq > 11 && freq < 16)
+ x = WD33C93_FS_12_15;
+ else if (freq > 15 && freq < 21)
+ x = WD33C93_FS_16_20;
+ else {
+ /* Hmm, wouldn't it be safer to assume highest freq here? */
+ x = WD33C93_FS_8_10;
+ freq = 8;
+ }
+ *mhz = freq;
+ return x;
+}
+
+/*
+ * to be used with the resync: fast: ... options
+ */
+static inline void set_resync ( struct WD33C93_hostdata *hd, int mask )
+{
+ int i;
+ for (i = 0; i < 8; i++)
+ if (mask & (1 << i))
+ hd->sync_stat[i] = SS_UNSET;
+}
+