-#define DRV_VERSION "1.1"
-
-/* Interrupt register offsets (from chip base address) */
-#define VSC_SATA_INT_STAT_OFFSET 0x00
-#define VSC_SATA_INT_MASK_OFFSET 0x04
-
-/* Taskfile registers offsets */
-#define VSC_SATA_TF_CMD_OFFSET 0x00
-#define VSC_SATA_TF_DATA_OFFSET 0x00
-#define VSC_SATA_TF_ERROR_OFFSET 0x04
-#define VSC_SATA_TF_FEATURE_OFFSET 0x06
-#define VSC_SATA_TF_NSECT_OFFSET 0x08
-#define VSC_SATA_TF_LBAL_OFFSET 0x0c
-#define VSC_SATA_TF_LBAM_OFFSET 0x10
-#define VSC_SATA_TF_LBAH_OFFSET 0x14
-#define VSC_SATA_TF_DEVICE_OFFSET 0x18
-#define VSC_SATA_TF_STATUS_OFFSET 0x1c
-#define VSC_SATA_TF_COMMAND_OFFSET 0x1d
-#define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
-#define VSC_SATA_TF_CTL_OFFSET 0x29
-
-/* DMA base */
-#define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
-#define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
-#define VSC_SATA_DMA_CMD_OFFSET 0x70
-
-/* SCRs base */
-#define VSC_SATA_SCR_STATUS_OFFSET 0x100
-#define VSC_SATA_SCR_ERROR_OFFSET 0x104
-#define VSC_SATA_SCR_CONTROL_OFFSET 0x108
-
-/* Port stride */
-#define VSC_SATA_PORT_OFFSET 0x200
-
-/* Error interrupt status bit offsets */
-#define VSC_SATA_INT_ERROR_E_OFFSET 2
-#define VSC_SATA_INT_ERROR_P_OFFSET 4
-#define VSC_SATA_INT_ERROR_T_OFFSET 5
-#define VSC_SATA_INT_ERROR_M_OFFSET 1
+#define DRV_VERSION "1.2"
+
+enum {
+ /* Interrupt register offsets (from chip base address) */
+ VSC_SATA_INT_STAT_OFFSET = 0x00,
+ VSC_SATA_INT_MASK_OFFSET = 0x04,
+
+ /* Taskfile registers offsets */
+ VSC_SATA_TF_CMD_OFFSET = 0x00,
+ VSC_SATA_TF_DATA_OFFSET = 0x00,
+ VSC_SATA_TF_ERROR_OFFSET = 0x04,
+ VSC_SATA_TF_FEATURE_OFFSET = 0x06,
+ VSC_SATA_TF_NSECT_OFFSET = 0x08,
+ VSC_SATA_TF_LBAL_OFFSET = 0x0c,
+ VSC_SATA_TF_LBAM_OFFSET = 0x10,
+ VSC_SATA_TF_LBAH_OFFSET = 0x14,
+ VSC_SATA_TF_DEVICE_OFFSET = 0x18,
+ VSC_SATA_TF_STATUS_OFFSET = 0x1c,
+ VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
+ VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
+ VSC_SATA_TF_CTL_OFFSET = 0x29,
+
+ /* DMA base */
+ VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
+ VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
+ VSC_SATA_DMA_CMD_OFFSET = 0x70,
+
+ /* SCRs base */
+ VSC_SATA_SCR_STATUS_OFFSET = 0x100,
+ VSC_SATA_SCR_ERROR_OFFSET = 0x104,
+ VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
+
+ /* Port stride */
+ VSC_SATA_PORT_OFFSET = 0x200,
+
+ /* Error interrupt status bit offsets */
+ VSC_SATA_INT_ERROR_CRC = 0x40,
+ VSC_SATA_INT_ERROR_T = 0x20,
+ VSC_SATA_INT_ERROR_P = 0x10,
+ VSC_SATA_INT_ERROR_R = 0x8,
+ VSC_SATA_INT_ERROR_E = 0x4,
+ VSC_SATA_INT_ERROR_M = 0x2,
+ VSC_SATA_INT_PHY_CHANGE = 0x1,
+ VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
+ VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
+ VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
+ VSC_SATA_INT_PHY_CHANGE),
+};
+
+