static s32 igb_set_default_fc(struct e1000_hw *hw);
static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
static s32 igb_set_default_fc(struct e1000_hw *hw);
static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
* @hw: pointer to the HW structure
*
* If a device specific structure was allocated, this function will
* @hw: pointer to the HW structure
*
* If a device specific structure was allocated, this function will
* @hw: pointer to the HW structure
*
* Determines and stores the system bus information for a particular
* @hw: pointer to the HW structure
*
* Determines and stores the system bus information for a particular
* @hw: pointer to the HW structure
*
* Clears the register array which contains the VLAN filter table by
* @hw: pointer to the HW structure
*
* Clears the register array which contains the VLAN filter table by
* @hw: pointer to the HW structure
* @offset: register offset in VLAN filter table
* @value: register value written to VLAN filter table
* @hw: pointer to the HW structure
* @offset: register offset in VLAN filter table
* @value: register value written to VLAN filter table
hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
/* Zero out the other (rar_entry_count - 1) receive addresses */
hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
/* Zero out the other (rar_entry_count - 1) receive addresses */
for (i = 1; i < rar_count; i++) {
array_wr32(E1000_RA, (i << 1), 0);
wrfl();
for (i = 1; i < rar_count; i++) {
array_wr32(E1000_RA, (i << 1), 0);
wrfl();
* @hw: pointer to the HW structure
*
* Checks the nvm for an alternate MAC address. An alternate MAC address
* @hw: pointer to the HW structure
*
* Checks the nvm for an alternate MAC address. An alternate MAC address
ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
&nvm_alt_mac_addr_offset);
if (ret_val) {
ret_val = hw->nvm.ops.read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
&nvm_alt_mac_addr_offset);
if (ret_val) {
offset = nvm_alt_mac_addr_offset + (i >> 1);
ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
if (ret_val) {
offset = nvm_alt_mac_addr_offset + (i >> 1);
ret_val = hw->nvm.ops.read_nvm(hw, offset, 1, &nvm_data);
if (ret_val) {
* @hw: pointer to the HW structure
* @addr: pointer to the receive address
* @index: receive address array register
* @hw: pointer to the HW structure
* @addr: pointer to the receive address
* @index: receive address array register
* @hw: pointer to the HW structure
* @mc_addr_list: array of multicast addresses to program
* @mc_addr_count: number of multicast addresses to program
* @hw: pointer to the HW structure
* @mc_addr_list: array of multicast addresses to program
* @mc_addr_count: number of multicast addresses to program
for (i = 0; i < hw->mac.mta_reg_count; i++) {
array_wr32(E1000_MTA, i, 0);
wrfl();
for (i = 0; i < hw->mac.mta_reg_count; i++) {
array_wr32(E1000_MTA, i, 0);
wrfl();
/* Load any remaining multicast addresses into the hash table. */
for (; mc_addr_count > 0; mc_addr_count--) {
hash_value = igb_hash_mc_addr(hw, mc_addr_list);
/* Load any remaining multicast addresses into the hash table. */
for (; mc_addr_count > 0; mc_addr_count--) {
hash_value = igb_hash_mc_addr(hw, mc_addr_list);
igb_mta_set(hw, hash_value);
mc_addr_list += ETH_ALEN;
}
}
/**
igb_mta_set(hw, hash_value);
mc_addr_list += ETH_ALEN;
}
}
/**
* @hw: pointer to the HW structure
*
* Clears the base hardware counters by reading the counter registers.
* @hw: pointer to the HW structure
*
* Clears the base hardware counters by reading the counter registers.
* @hw: pointer to the HW structure
*
* Checks to see of the link status of the hardware has changed. If a
* @hw: pointer to the HW structure
*
* Checks to see of the link status of the hardware has changed. If a
* @hw: pointer to the HW structure
*
* Determines which flow control settings to use, then configures flow
* @hw: pointer to the HW structure
*
* Determines which flow control settings to use, then configures flow
/* Call the necessary media_type subroutine to configure the link. */
ret_val = hw->mac.ops.setup_physical_interface(hw);
/* Call the necessary media_type subroutine to configure the link. */
ret_val = hw->mac.ops.setup_physical_interface(hw);
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
wr32(E1000_FCT, FLOW_CONTROL_TYPE);
wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
wr32(E1000_FCT, FLOW_CONTROL_TYPE);
wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
* @hw: pointer to the HW structure
*
* Configures the collision distance to the default value and is used
* @hw: pointer to the HW structure
*
* Configures the collision distance to the default value and is used
* @hw: pointer to the HW structure
*
* Sets the flow control high/low threshold (watermark) registers. If
* @hw: pointer to the HW structure
*
* Sets the flow control high/low threshold (watermark) registers. If
* @hw: pointer to the HW structure
*
* Read the EEPROM for the default values for flow control and store the
* @hw: pointer to the HW structure
*
* Read the EEPROM for the default values for flow control and store the
* @hw: pointer to the HW structure
*
* Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
* @hw: pointer to the HW structure
*
* Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
* 3: Both Rx and TX flow control (symmetric) is enabled.
* other: No other values should be possible at this point.
*/
* 3: Both Rx and TX flow control (symmetric) is enabled.
* other: No other values should be possible at this point.
*/
* @hw: pointer to the HW structure
*
* Checks the status of auto-negotiation after link up to ensure that the
* @hw: pointer to the HW structure
*
* Checks the status of auto-negotiation after link up to ensure that the
- hw_dbg(hw, "Flow Control = "
- "RX PAUSE frames only.\r\n");
+ hw_dbg("Flow Control = "
+ "RX PAUSE frames only.\r\n");
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc.type = e1000_fc_tx_pause;
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc.type = e1000_fc_tx_pause;
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc.type = e1000_fc_rx_pause;
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
hw->fc.type = e1000_fc_rx_pause;
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
ret_val = hw->nvm.ops.read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
if (ret_val) {
* @hw: pointer to the HW structure
*
* Remove the current LED configuration and set the LED configuration
* @hw: pointer to the HW structure
*
* Remove the current LED configuration and set the LED configuration
* @hw: pointer to the HW structure
*
* Returns 0 (0) if successful, else returns -10
* @hw: pointer to the HW structure
*
* Returns 0 (0) if successful, else returns -10
* @hw: pointer to the HW structure
*
* Reset the Adaptive Interframe Spacing throttle to default values.
* @hw: pointer to the HW structure
*
* Reset the Adaptive Interframe Spacing throttle to default values.
* @hw: pointer to the HW structure
*
* Update the Adaptive Interframe Spacing Throttle value based on the
* @hw: pointer to the HW structure
*
* Update the Adaptive Interframe Spacing Throttle value based on the
* @hw: pointer to the HW structure
*
* Verify that when not using auto-negotitation that MDI/MDIx is correctly
* @hw: pointer to the HW structure
*
* Verify that when not using auto-negotitation that MDI/MDIx is correctly
* @hw: pointer to the HW structure
* @reg: 32bit register offset such as E1000_SCTL
* @offset: register offset to write to
* @hw: pointer to the HW structure
* @reg: 32bit register offset such as E1000_SCTL
* @offset: register offset to write to
* @hw: pointer to the HW structure
*
* Verifies the hardware needs to allow ARPs to be processed by the host.
* @hw: pointer to the HW structure
*
* Verifies the hardware needs to allow ARPs to be processed by the host.