+
+ return plb;
+}
+
+static void eplike_fixup_uart_clk(int index, const char *path,
+ unsigned int ser_clk,
+ unsigned int plb_clk)
+{
+ unsigned int sdr;
+ unsigned int clock;
+
+ switch (index) {
+ case 0:
+ sdr = SDR0_READ(DCRN_SDR0_UART0);
+ break;
+ case 1:
+ sdr = SDR0_READ(DCRN_SDR0_UART1);
+ break;
+ case 2:
+ sdr = SDR0_READ(DCRN_SDR0_UART2);
+ break;
+ case 3:
+ sdr = SDR0_READ(DCRN_SDR0_UART3);
+ break;
+ default:
+ return;
+ }
+
+ if (sdr & 0x00800000u)
+ clock = ser_clk;
+ else
+ clock = plb_clk / __fix_zero(sdr & 0xff, 256);
+
+ dt_fixup_clock(path, clock);
+}
+
+void ibm440ep_fixup_clocks(unsigned int sys_clk,
+ unsigned int ser_clk,
+ unsigned int tmr_clk)
+{
+ unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
+
+ /* serial clocks beed fixup based on int/ext */
+ eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
+}
+
+void ibm440gx_fixup_clocks(unsigned int sys_clk,
+ unsigned int ser_clk,
+ unsigned int tmr_clk)
+{
+ unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
+
+ /* serial clocks beed fixup based on int/ext */
+ eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
+}
+
+void ibm440spe_fixup_clocks(unsigned int sys_clk,
+ unsigned int ser_clk,
+ unsigned int tmr_clk)
+{
+ unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
+
+ /* serial clocks beed fixup based on int/ext */
+ eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
+}
+
+void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
+{
+ u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
+ u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
+ u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
+ u32 psr = mfdcr(DCRN_405_CPC0_PSR);
+ u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
+ u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
+
+ fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
+ fbdv = (pllmr & 0x1e000000) >> 25;
+ if (fbdv == 0)
+ fbdv = 16;
+ cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
+ opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
+ ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
+ epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
+ udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
+
+ /* check for 405GPr */
+ if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
+ fwdvb = 8 - (pllmr & 0x00000007);
+ if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
+ if (psr & 0x00000020) /* New mode enable */
+ m = fwdvb * 2 * ppdv;
+ else
+ m = fwdvb * cbdv * ppdv;
+ else if (psr & 0x00000020) /* New mode enable */
+ if (psr & 0x00000800) /* PerClk synch mode */
+ m = fwdvb * 2 * epdv;
+ else
+ m = fbdv * fwdv;
+ else if (epdv == fbdv)
+ m = fbdv * cbdv * epdv;
+ else
+ m = fbdv * fwdvb * cbdv;
+
+ cpu = sys_clk * m / fwdv;
+ plb = sys_clk * m / (fwdvb * cbdv);
+ } else {
+ m = fwdv * fbdv * cbdv;
+ cpu = sys_clk * m / fwdv;
+ plb = cpu / cbdv;
+ }
+ opb = plb / opdv;
+ ebc = plb / epdv;
+
+ if (cpc0_cr0 & 0x80)
+ /* uart0 uses the external clock */
+ uart0 = ser_clk;
+ else
+ uart0 = cpu / udiv;
+
+ if (cpc0_cr0 & 0x40)
+ /* uart1 uses the external clock */
+ uart1 = ser_clk;
+ else
+ uart1 = cpu / udiv;
+
+ /* setup the timebase clock to tick at the cpu frequency */
+ cpc0_cr1 = cpc0_cr1 & ~0x00800000;
+ mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
+ tb = cpu;
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/ebc", ebc);
+ dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
+}
+
+
+void ibm405ep_fixup_clocks(unsigned int sys_clk)
+{
+ u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
+ u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
+ u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
+ u32 cpu, plb, opb, ebc, uart0, uart1;
+ u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
+ u32 pllmr0_ccdv, tb, m;
+
+ fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
+ fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
+ fbdv = (pllmr1 & 0x00f00000) >> 20;
+ if (fbdv == 0)
+ fbdv = 16;
+
+ cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
+ epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
+ opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
+
+ m = fbdv * fwdvb;
+
+ pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
+ if (pllmr1 & 0x80000000)
+ cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
+ else
+ cpu = sys_clk / pllmr0_ccdv;
+
+ plb = cpu / cbdv;
+ opb = plb / opdv;
+ ebc = plb / epdv;
+ tb = cpu;
+ uart0 = cpu / (cpc0_ucr & 0x0000007f);
+ uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/ebc", ebc);