2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
5 * Based entirely upon drivers/sbus/audio/dbri.c which is:
6 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
7 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
9 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
10 * on Sun SPARCstation 10, 20, LX and Voyager models.
12 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
13 * data time multiplexer with ISDN support (aka T7259)
14 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
15 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
17 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
18 * Sparc Technology Business (courtesy of Sun Support)
19 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
20 * available from the Lucent (formarly AT&T microelectronics) home
22 * - http://www.freesoft.org/Linux/DBRI/
23 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
24 * Interfaces: CHI, Audio In & Out, 2 bits parallel
25 * Documentation: from the Crystal Semiconductor home page.
27 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
28 * memory and a serial device (long pipes, nr 0-15) or between two serial
29 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
30 * device (short pipes).
31 * A timeslot defines the bit-offset and nr of bits read from a serial device.
32 * The timeslots are linked to 6 circular lists, one for each direction for
33 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
34 * (the second one is a monitor/tee pipe, valid only for serial input).
36 * The mmcodec is connected via the CHI bus and needs the data & some
37 * parameters (volume, output selection) timemultiplexed in 8 byte
38 * chunks. It also has a control mode, which serves for audio format setting.
40 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
41 * the same CHI bus, so I thought perhaps it is possible to use the onboard
42 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
43 * audio devices. But the SUN HW group decided against it, at least on my
44 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * I've tried to stick to the following function naming conventions:
49 * cs4215_* CS4215 codec specific stuff
50 * dbri_* DBRI high-level stuff
51 * other DBRI low-level stuff
54 #include <sound/driver.h>
55 #include <linux/interrupt.h>
56 #include <linux/delay.h>
58 #include <sound/core.h>
59 #include <sound/pcm.h>
60 #include <sound/pcm_params.h>
61 #include <sound/info.h>
62 #include <sound/control.h>
63 #include <sound/initval.h>
68 #include <asm/atomic.h>
70 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
71 MODULE_DESCRIPTION("Sun DBRI");
72 MODULE_LICENSE("GPL");
73 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
95 static int dbri_debug;
96 module_param(dbri_debug, int, 0644);
97 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
100 static char *cmds[] = {
101 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
102 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
105 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
108 #define dprintk(a, x...)
110 #endif /* DBRI_DEBUG */
112 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
116 /***************************************************************************
117 CS4215 specific definitions and structures
118 ****************************************************************************/
121 __u8 data[4]; /* Data mode: Time slots 5-8 */
122 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
124 __u8 offset; /* Bit offset from frame sync to time slot 1 */
125 volatile __u32 status;
126 volatile __u32 version;
127 __u8 precision; /* In bits, either 8 or 16 */
128 __u8 channels; /* 1 or 2 */
135 /* Time Slot 1, Status register */
136 #define CS4215_CLB (1<<2) /* Control Latch Bit */
137 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
138 /* 0: line: 2.8V, speaker 8V */
139 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
140 #define CS4215_RSRVD_1 (1<<5)
142 /* Time Slot 2, Data Format Register */
143 #define CS4215_DFR_LINEAR16 0
144 #define CS4215_DFR_ULAW 1
145 #define CS4215_DFR_ALAW 2
146 #define CS4215_DFR_LINEAR8 3
147 #define CS4215_DFR_STEREO (1<<2)
153 { 8000, (1 << 4), (0 << 3) },
154 { 16000, (1 << 4), (1 << 3) },
155 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
156 { 32000, (1 << 4), (3 << 3) },
157 /* { NA, (1 << 4), (4 << 3) }, */
158 /* { NA, (1 << 4), (5 << 3) }, */
159 { 48000, (1 << 4), (6 << 3) },
160 { 9600, (1 << 4), (7 << 3) },
161 { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
162 { 11025, (2 << 4), (1 << 3) },
163 { 18900, (2 << 4), (2 << 3) },
164 { 22050, (2 << 4), (3 << 3) },
165 { 37800, (2 << 4), (4 << 3) },
166 { 44100, (2 << 4), (5 << 3) },
167 { 33075, (2 << 4), (6 << 3) },
168 { 6615, (2 << 4), (7 << 3) },
172 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
174 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
176 /* Time Slot 3, Serial Port Control register */
177 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
178 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
179 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
180 #define CS4215_BSEL_128 (1<<2)
181 #define CS4215_BSEL_256 (2<<2)
182 #define CS4215_MCK_MAST (0<<4) /* Master clock */
183 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
184 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
185 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
186 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
188 /* Time Slot 4, Test Register */
189 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
190 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
192 /* Time Slot 5, Parallel Port Register */
193 /* Read only here and the same as the in data mode */
195 /* Time Slot 6, Reserved */
197 /* Time Slot 7, Version Register */
198 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
200 /* Time Slot 8, Reserved */
205 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
207 /* Time Slot 5, Output Setting */
208 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
209 #define CS4215_LE (1<<6) /* Line Out Enable */
210 #define CS4215_HE (1<<7) /* Headphone Enable */
212 /* Time Slot 6, Output Setting */
213 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
214 #define CS4215_SE (1<<6) /* Speaker Enable */
215 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
217 /* Time Slot 7, Input Setting */
218 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
219 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
220 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
221 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
222 #define CS4215_PIO1 (1<<7)
224 /* Time Slot 8, Input Setting */
225 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
226 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
228 /***************************************************************************
229 DBRI specific definitions and structures
230 ****************************************************************************/
232 /* DBRI main registers */
233 #define REG0 0x00UL /* Status and Control */
234 #define REG1 0x04UL /* Mode and Interrupt */
235 #define REG2 0x08UL /* Parallel IO */
236 #define REG3 0x0cUL /* Test */
237 #define REG8 0x20UL /* Command Queue Pointer */
238 #define REG9 0x24UL /* Interrupt Queue Pointer */
240 #define DBRI_NO_CMDS 64
241 #define DBRI_INT_BLK 64
242 #define DBRI_NO_DESCS 64
243 #define DBRI_NO_PIPES 32
244 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
248 #define DBRI_NO_STREAMS 2
250 /* One transmit/receive descriptor */
251 /* When ba != 0 descriptor is used */
253 volatile __u32 word1;
254 __u32 ba; /* Transmit/Receive Buffer Address */
255 __u32 nda; /* Next Descriptor Address */
256 volatile __u32 word4;
259 /* This structure is in a DMA region where it can accessed by both
260 * the CPU and the DBRI
263 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
264 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
265 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
268 #define dbri_dma_off(member, elem) \
269 ((u32)(unsigned long) \
270 (&(((struct dbri_dma *)0)->member[elem])))
272 enum in_or_out { PIPEinput, PIPEoutput };
275 u32 sdp; /* SDP command word */
276 int nextpipe; /* Next pipe in linked list */
277 int length; /* Length of timeslot (bits) */
278 int first_desc; /* Index of first descriptor */
279 int desc; /* Index of active descriptor */
280 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
283 /* Per stream (playback or record) information */
284 struct dbri_streaminfo {
285 struct snd_pcm_substream *substream;
286 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
287 int left; /* # of bytes left in DMA buffer */
288 int size; /* Size of DMA buffer */
289 size_t offset; /* offset in user buffer */
290 int pipe; /* Data pipe used */
291 int left_gain; /* mixer elements */
295 /* This structure holds the information for both chips (DBRI & CS4215) */
297 struct snd_card *card; /* ALSA card */
299 int regs_size, irq; /* Needed for unload */
300 struct sbus_dev *sdev; /* SBUS device info */
303 struct dbri_dma *dma; /* Pointer to our DMA block */
304 u32 dma_dvma; /* DBRI visible DMA address */
306 void __iomem *regs; /* dbri HW regs */
307 int dbri_irqp; /* intr queue pointer */
308 int wait_send; /* sequence of command buffers send */
309 int wait_ackd; /* sequence of command buffers acknowledged */
311 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
312 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
316 struct cs4215 mm; /* mmcodec special info */
317 /* per stream (playback/record) info */
318 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
320 struct snd_dbri *next;
323 #define DBRI_MAX_VOLUME 63 /* Output volume */
324 #define DBRI_MAX_GAIN 15 /* Input gain */
326 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
327 #define D_P (1<<15) /* Program command & queue pointer valid */
328 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
329 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
330 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
331 #define D_X (1<<7) /* Sanity Timer Disable */
332 #define D_T (1<<6) /* Permit activation of the TE interface */
333 #define D_N (1<<5) /* Permit activation of the NT interface */
334 #define D_C (1<<4) /* Permit activation of the CHI interface */
335 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
336 #define D_D (1<<2) /* Disable Master Mode */
337 #define D_H (1<<1) /* Halt for Analysis */
338 #define D_R (1<<0) /* Soft Reset */
340 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
341 #define D_LITTLE_END (1<<8) /* Byte Order */
342 #define D_BIG_END (0<<8) /* Byte Order */
343 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
344 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
345 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
346 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
347 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
349 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
350 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
351 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
352 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
353 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
354 #define D_ENPIO (0xf0) /* Enable all the pins */
355 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
356 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
357 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
358 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
360 /* DBRI Commands (Page 20) */
361 #define D_WAIT 0x0 /* Stop execution */
362 #define D_PAUSE 0x1 /* Flush long pipes */
363 #define D_JUMP 0x2 /* New command queue */
364 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
365 #define D_REX 0x4 /* Report command execution via interrupt */
366 #define D_SDP 0x5 /* Setup Data Pipe */
367 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
368 #define D_DTS 0x7 /* Define Time Slot */
369 #define D_SSP 0x8 /* Set short Data Pipe */
370 #define D_CHI 0x9 /* Set CHI Global Mode */
371 #define D_NT 0xa /* NT Command */
372 #define D_TE 0xb /* TE Command */
373 #define D_CDEC 0xc /* Codec setup */
374 #define D_TEST 0xd /* No comment */
375 #define D_CDM 0xe /* CHI Data mode command */
377 /* Special bits for some commands */
378 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
380 /* Setup Data Pipe */
382 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
383 #define D_SDP_CHANGE (2<<18) /* Report any changes */
384 #define D_SDP_EVERY (3<<18) /* Report any changes */
385 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
386 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
389 #define D_SDP_MEM (0<<13) /* To/from memory */
390 #define D_SDP_HDLC (2<<13)
391 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
392 #define D_SDP_SER (4<<13) /* Serial to serial */
393 #define D_SDP_FIXED (6<<13) /* Short only */
394 #define D_SDP_MODE(v) ((v)&(7<<13))
396 #define D_SDP_TO_SER (1<<12) /* Direction */
397 #define D_SDP_FROM_SER (0<<12) /* Direction */
398 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
399 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
400 #define D_SDP_P (1<<10) /* Pointer Valid */
401 #define D_SDP_A (1<<8) /* Abort */
402 #define D_SDP_C (1<<7) /* Clear */
404 /* Define Time Slot */
405 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
406 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
407 #define D_DTS_INS (1<<15) /* Insert Time Slot */
408 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
409 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
410 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
412 /* Time Slot defines */
413 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
414 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
415 #define D_TS_DI (1<<13) /* Data Invert */
416 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
417 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
418 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
419 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
420 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
421 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
423 /* Concentration Highway Interface Modes */
424 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
425 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
426 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
427 #define D_CHI_OD (1<<13) /* Open Drain Enable */
428 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
429 #define D_CHI_FD (1<<11) /* Frame Drive */
430 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
432 /* NT: These are here for completeness */
433 #define D_NT_FBIT (1<<17) /* Frame Bit */
434 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
435 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
436 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
437 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
438 #define D_NT_FT (1<<12) /* Fixed Timing */
439 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
440 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
441 #define D_NT_ACT (1<<9) /* Activate Interface */
442 #define D_NT_MFE (1<<8) /* Multiframe Enable */
443 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
444 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
445 #define D_NT_FACT (1<<1) /* Force Activation */
446 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
449 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
450 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
451 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
454 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
455 #define D_TEST_SIZE(v) ((v)<<11) /* */
456 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
457 #define D_TEST_PROC 0x6 /* MicroProcessor test */
458 #define D_TEST_SER 0x7 /* Serial-Controller test */
459 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
460 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
461 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
462 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
463 #define D_TEST_DUMP 0xe /* ROM Dump */
466 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
467 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
468 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
469 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
470 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
471 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
474 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
475 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
476 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
477 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
478 #define D_INTR_EOL 5 /* End of List */
479 #define D_INTR_CMDI 6 /* Command has bean read */
480 #define D_INTR_XCMP 8 /* Transmission of frame complete */
481 #define D_INTR_SBRI 9 /* BRI status change info */
482 #define D_INTR_FXDT 10 /* Fixed data change */
483 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
484 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
485 #define D_INTR_DBYT 12 /* Dropped by frame slip */
486 #define D_INTR_RBYT 13 /* Repeated by frame slip */
487 #define D_INTR_LINT 14 /* Lost Interrupt */
488 #define D_INTR_UNDR 15 /* DMA underrun */
492 #define D_INTR_CHI 36
493 #define D_INTR_CMD 38
495 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
496 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
497 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
498 #define D_INTR_GETVAL(v) ((v) & 0xffff)
499 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
501 #define D_P_0 0 /* TE receive anchor */
502 #define D_P_1 1 /* TE transmit anchor */
503 #define D_P_2 2 /* NT transmit anchor */
504 #define D_P_3 3 /* NT receive anchor */
505 #define D_P_4 4 /* CHI send data */
506 #define D_P_5 5 /* CHI receive data */
507 #define D_P_6 6 /* */
508 #define D_P_7 7 /* */
509 #define D_P_8 8 /* */
510 #define D_P_9 9 /* */
511 #define D_P_10 10 /* */
512 #define D_P_11 11 /* */
513 #define D_P_12 12 /* */
514 #define D_P_13 13 /* */
515 #define D_P_14 14 /* */
516 #define D_P_15 15 /* */
517 #define D_P_16 16 /* CHI anchor pipe */
518 #define D_P_17 17 /* CHI send */
519 #define D_P_18 18 /* CHI receive */
520 #define D_P_19 19 /* CHI receive */
521 #define D_P_20 20 /* CHI receive */
522 #define D_P_21 21 /* */
523 #define D_P_22 22 /* */
524 #define D_P_23 23 /* */
525 #define D_P_24 24 /* */
526 #define D_P_25 25 /* */
527 #define D_P_26 26 /* */
528 #define D_P_27 27 /* */
529 #define D_P_28 28 /* */
530 #define D_P_29 29 /* */
531 #define D_P_30 30 /* */
532 #define D_P_31 31 /* */
534 /* Transmit descriptor defines */
535 #define DBRI_TD_F (1<<31) /* End of Frame */
536 #define DBRI_TD_D (1<<30) /* Do not append CRC */
537 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
538 #define DBRI_TD_B (1<<15) /* Final interrupt */
539 #define DBRI_TD_M (1<<14) /* Marker interrupt */
540 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
541 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
542 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
543 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
544 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
545 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
546 /* Maximum buffer size per TD: almost 8Kb */
547 #define DBRI_TD_MAXCNT ((1 << 13) - 1)
549 /* Receive descriptor defines */
550 #define DBRI_RD_F (1<<31) /* End of Frame */
551 #define DBRI_RD_C (1<<30) /* Completed buffer */
552 #define DBRI_RD_B (1<<15) /* Final interrupt */
553 #define DBRI_RD_M (1<<14) /* Marker interrupt */
554 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
555 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
556 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
557 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
558 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
559 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
560 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
562 /* stream_info[] access */
563 /* Translate the ALSA direction into the array index */
564 #define DBRI_STREAMNO(substream) \
565 (substream->stream == \
566 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
568 /* Return a pointer to dbri_streaminfo */
569 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
571 static struct snd_dbri *dbri_list; /* All DBRI devices */
574 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
575 * So we have to reverse the bits. Note: not all bit lengths are supported
577 static __u32 reverse_bytes(__u32 b, int len)
581 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
583 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
585 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
587 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
589 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
594 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
601 ****************************************************************************
602 ************** DBRI initialization and command synchronization *************
603 ****************************************************************************
605 Commands are sent to the DBRI by building a list of them in memory,
606 then writing the address of the first list item to DBRI register 8.
607 The list is terminated with a WAIT command, which generates a
608 CPU interrupt to signal completion.
610 Since the DBRI can run in parallel with the CPU, several means of
611 synchronization present themselves. The method implemented here is close
612 to the original scheme (Rudolf's), and uses 2 counters (wait_send and
613 wait_ackd) to synchronize the command buffer between the CPU and the DBRI.
615 A more sophisticated scheme might involve a circular command buffer
616 or an array of command buffers. A routine could fill one with
617 commands and link it onto a list. When a interrupt signaled
618 completion of the current command buffer, look on the list for
621 Every time a routine wants to write commands to the DBRI, it must
622 first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
623 in return. dbri_cmdlock() will block if the previous commands have not
624 been completed yet. After this the commands can be written to the buffer,
625 and dbri_cmdsend() is called with the final pointer value to send them
630 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri);
632 enum dbri_lock { NoGetLock, GetLock };
635 static volatile s32 *dbri_cmdlock(struct snd_dbri * dbri, enum dbri_lock get)
637 int maxloops = MAXLOOPS;
640 if ((get == GetLock) && spin_is_locked(&dbri->lock)) {
641 printk(KERN_ERR "DBRI: cmdlock called while in spinlock.");
645 /* Delay if previous commands are still being processed */
646 while ((--maxloops) > 0 && (dbri->wait_send != dbri->wait_ackd)) {
647 msleep_interruptible(1);
650 printk(KERN_ERR "DBRI: Chip never completed command buffer %d\n",
653 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
654 MAXLOOPS - maxloops - 1);
657 /*if (get == GetLock) spin_lock(&dbri->lock); */
658 return &dbri->dma->cmd[0];
661 static void dbri_cmdsend(struct snd_dbri * dbri, volatile s32 * cmd)
665 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
666 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
669 if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) {
670 printk(KERN_ERR "DBRI: Command buffer overflow! (bug in driver)\n");
671 /* Ignore the last part. */
672 cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3];
676 dbri->wait_send &= 0xffff; /* restrict it to a 16 bit counter. */
677 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
678 *(cmd++) = DBRI_CMD(D_WAIT, 1, dbri->wait_send);
680 /* Set command pointer and signal it is valid. */
681 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
683 /*spin_unlock(&dbri->lock); */
686 /* Lock must be held when calling this */
687 static void dbri_reset(struct snd_dbri * dbri)
692 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
693 sbus_readl(dbri->regs + REG0),
694 sbus_readl(dbri->regs + REG2),
695 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
697 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
698 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
701 /* A brute approach - DBRI falls back to working burst size by itself
702 * On SS20 D_S does not work, so do not try so high. */
703 tmp = sbus_readl(dbri->regs + REG0);
706 sbus_writel(tmp, dbri->regs + REG0);
709 /* Lock must not be held before calling this */
710 static void dbri_initialize(struct snd_dbri * dbri)
717 spin_lock_irqsave(&dbri->lock, flags);
721 cmd = dbri_cmdlock(dbri, NoGetLock);
722 dprintk(D_GEN, "init: cmd: %p, int: %p\n",
723 &dbri->dma->cmd[0], &dbri->dma->intr[0]);
725 /* Initialize pipes */
726 for (n = 0; n < DBRI_NO_PIPES; n++)
727 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
730 * Initialize the interrupt ringbuffer.
732 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
733 dbri->dma->intr[0] = dma_addr;
736 * Set up the interrupt queue
738 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
741 dbri_cmdsend(dbri, cmd);
742 spin_unlock_irqrestore(&dbri->lock, flags);
746 ****************************************************************************
747 ************************** DBRI data pipe management ***********************
748 ****************************************************************************
750 While DBRI control functions use the command and interrupt buffers, the
751 main data path takes the form of data pipes, which can be short (command
752 and interrupt driven), or long (attached to DMA buffers). These functions
753 provide a rudimentary means of setting up and managing the DBRI's pipes,
754 but the calling functions have to make sure they respect the pipes' linked
755 list ordering, among other things. The transmit and receive functions
756 here interface closely with the transmit and receive interrupt code.
759 static int pipe_active(struct snd_dbri * dbri, int pipe)
761 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
764 /* reset_pipe(dbri, pipe)
766 * Called on an in-use pipe to clear anything being transmitted or received
767 * Lock must be held before calling this.
769 static void reset_pipe(struct snd_dbri * dbri, int pipe)
775 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
776 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
780 sdp = dbri->pipes[pipe].sdp;
782 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
786 cmd = dbri_cmdlock(dbri, NoGetLock);
787 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
789 dbri_cmdsend(dbri, cmd);
791 desc = dbri->pipes[pipe].first_desc;
793 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
794 desc = dbri->next_desc[desc];
797 dbri->pipes[pipe].desc = -1;
798 dbri->pipes[pipe].first_desc = -1;
801 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
803 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
804 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
808 if ((sdp & 0xf800) != sdp) {
809 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
813 /* If this is a fixed receive pipe, arrange for an interrupt
814 * every time its data changes
816 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
820 dbri->pipes[pipe].sdp = sdp;
821 dbri->pipes[pipe].desc = -1;
822 dbri->pipes[pipe].first_desc = -1;
824 reset_pipe(dbri, pipe);
827 static void link_time_slot(struct snd_dbri * dbri, int pipe,
828 int prevpipe, int nextpipe,
829 int length, int cycle)
834 if (pipe < 0 || pipe > DBRI_MAX_PIPE
835 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
836 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
838 "DBRI: link_time_slot called with illegal pipe number\n");
842 if (dbri->pipes[pipe].sdp == 0
843 || dbri->pipes[prevpipe].sdp == 0
844 || dbri->pipes[nextpipe].sdp == 0) {
845 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
849 dbri->pipes[prevpipe].nextpipe = pipe;
851 dbri->pipes[pipe].nextpipe = nextpipe;
852 dbri->pipes[pipe].length = length;
854 cmd = dbri_cmdlock(dbri, NoGetLock);
856 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
857 /* Deal with CHI special case:
858 * "If transmission on edges 0 or 1 is desired, then cycle n
859 * (where n = # of bit times per frame...) must be used."
860 * - DBRI data sheet, page 11
862 if (prevpipe == 16 && cycle == 0)
863 cycle = dbri->chi_bpf;
865 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
866 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
869 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
871 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
872 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
874 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
878 dbri_cmdsend(dbri, cmd);
881 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
882 enum in_or_out direction, int prevpipe,
888 if (pipe < 0 || pipe > DBRI_MAX_PIPE
889 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE) {
891 "DBRI: unlink_time_slot called with illegal pipe number\n");
895 cmd = dbri_cmdlock(dbri, NoGetLock);
897 if (direction == PIPEinput) {
898 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
899 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
900 *(cmd++) = D_TS_NEXT(nextpipe);
903 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
904 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
906 *(cmd++) = D_TS_NEXT(nextpipe);
909 dbri_cmdsend(dbri, cmd);
912 /* xmit_fixed() / recv_fixed()
914 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
915 * expected to change much, and which we don't need to buffer.
916 * The DBRI only interrupts us when the data changes (receive pipes),
917 * or only changes the data when this function is called (transmit pipes).
918 * Only short pipes (numbers 16-31) can be used in fixed data mode.
920 * These function operate on a 32-bit field, no matter how large
921 * the actual time slot is. The interrupt handler takes care of bit
922 * ordering and alignment. An 8-bit time slot will always end up
923 * in the low-order 8 bits, filled either MSB-first or LSB-first,
924 * depending on the settings passed to setup_pipe()
926 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
930 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
931 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
935 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
936 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
940 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
941 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
945 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
946 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
950 /* DBRI short pipes always transmit LSB first */
952 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
953 data = reverse_bytes(data, dbri->pipes[pipe].length);
955 cmd = dbri_cmdlock(dbri, GetLock);
957 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
960 dbri_cmdsend(dbri, cmd);
963 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
965 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
966 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
970 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
971 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
975 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
976 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
980 dbri->pipes[pipe].recv_fixed_ptr = ptr;
985 * Setup transmit/receive data on a "long" pipe - i.e, one associated
988 * Only pipe numbers 0-15 can be used in this mode.
990 * This function takes a stream number pointing to a data buffer,
991 * and work by building chains of descriptors which identify the
992 * data buffers. Buffers too large for a single descriptor will
993 * be spread across multiple descriptors.
995 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
997 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1001 int first_desc = -1;
1004 if (info->pipe < 0 || info->pipe > 15) {
1005 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1009 if (dbri->pipes[info->pipe].sdp == 0) {
1010 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1015 dvma_buffer = info->dvma_buffer;
1018 if (streamno == DBRI_PLAY) {
1019 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1020 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1025 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1027 "DBRI: setup_descs: Called on transmit pipe %d\n",
1031 /* Should be able to queue multiple buffers to receive on a pipe */
1032 if (pipe_active(dbri, info->pipe)) {
1033 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1038 /* Make sure buffer size is multiple of four */
1045 for (; desc < DBRI_NO_DESCS; desc++) {
1046 if (!dbri->dma->desc[desc].ba)
1049 if (desc == DBRI_NO_DESCS) {
1050 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1054 if (len > DBRI_TD_MAXCNT) {
1055 mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */
1059 if (mylen > period) {
1063 dbri->next_desc[desc] = -1;
1064 dbri->dma->desc[desc].ba = dvma_buffer;
1065 dbri->dma->desc[desc].nda = 0;
1067 if (streamno == DBRI_PLAY) {
1068 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1069 dbri->dma->desc[desc].word4 = 0;
1070 if (first_desc != -1)
1071 dbri->dma->desc[desc].word1 |= DBRI_TD_M;
1073 dbri->dma->desc[desc].word1 = 0;
1074 dbri->dma->desc[desc].word4 =
1075 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1078 if (first_desc == -1) {
1081 dbri->next_desc[last_desc] = desc;
1082 dbri->dma->desc[last_desc].nda =
1083 dbri->dma_dvma + dbri_dma_off(desc, desc);
1087 dvma_buffer += mylen;
1091 if (first_desc == -1 || last_desc == -1) {
1092 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1096 dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M;
1097 if (streamno == DBRI_PLAY) {
1098 dbri->dma->desc[last_desc].word1 |=
1099 DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
1101 dbri->pipes[info->pipe].first_desc = first_desc;
1102 dbri->pipes[info->pipe].desc = first_desc;
1104 for (desc = first_desc; desc != -1; desc = dbri->next_desc[desc]) {
1105 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1107 dbri->dma->desc[desc].word1,
1108 dbri->dma->desc[desc].ba,
1109 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1115 ****************************************************************************
1116 ************************** DBRI - CHI interface ****************************
1117 ****************************************************************************
1119 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1120 multiplexed serial interface which the DBRI can operate in either master
1121 (give clock/frame sync) or slave (take clock/frame sync) mode.
1125 enum master_or_slave { CHImaster, CHIslave };
1127 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1132 static int chi_initialized = 0; /* FIXME: mutex? */
1134 if (!chi_initialized) {
1136 cmd = dbri_cmdlock(dbri, GetLock);
1138 /* Set CHI Anchor: Pipe 16 */
1140 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1141 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1142 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1143 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1144 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1146 dbri->pipes[16].sdp = 1;
1147 dbri->pipes[16].nextpipe = 16;
1155 for (pipe = 0; pipe < DBRI_NO_PIPES; pipe++ )
1157 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER)
1158 unlink_time_slot(dbri, pipe, PIPEoutput,
1159 16, dbri->pipes[pipe].nextpipe);
1161 unlink_time_slot(dbri, pipe, PIPEinput,
1162 16, dbri->pipes[pipe].nextpipe);
1165 cmd = dbri_cmdlock(dbri, GetLock);
1168 if (master_or_slave == CHIslave) {
1169 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1171 * CHICM = 0 (slave mode, 8 kHz frame rate)
1172 * IR = give immediate CHI status interrupt
1173 * EN = give CHI status interrupt upon change
1175 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1177 /* Setup DBRI for CHI Master - generate clock, FS
1179 * BPF = bits per 8 kHz frame
1180 * 12.288 MHz / CHICM_divisor = clock rate
1181 * FD = 1 - drive CHIFS on rising edge of CHICK
1183 int clockrate = bits_per_frame * 8;
1184 int divisor = 12288 / clockrate;
1186 if (divisor > 255 || divisor * clockrate != 12288)
1187 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1189 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1190 | D_CHI_BPF(bits_per_frame));
1193 dbri->chi_bpf = bits_per_frame;
1197 * RCE = 0 - receive on falling edge of CHICK
1198 * XCE = 1 - transmit on rising edge of CHICK
1199 * XEN = 1 - enable transmitter
1200 * REN = 1 - enable receiver
1203 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1204 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1206 dbri_cmdsend(dbri, cmd);
1210 ****************************************************************************
1211 *********************** CS4215 audio codec management **********************
1212 ****************************************************************************
1214 In the standard SPARC audio configuration, the CS4215 codec is attached
1215 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1218 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1222 * Pipe 4: Send timeslots 1-4 (audio data)
1223 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1224 * Pipe 6: Receive timeslots 1-4 (audio data)
1225 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1226 * interrupt, and the rest of the data (slot 5 and 8) is
1227 * not relevant for us (only for doublechecking).
1230 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1231 * Pipe 18: Receive timeslot 1 (clb).
1232 * Pipe 19: Receive timeslot 7 (version).
1235 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1236 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1237 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1238 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1240 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1241 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1242 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1245 static int cs4215_init_data(struct cs4215 *mm)
1248 * No action, memory resetting only.
1250 * Data Time Slot 5-8
1251 * Speaker,Line and Headphone enable. Gain set to the half.
1254 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1255 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1256 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1257 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1260 * Control Time Slot 1-4
1261 * 0: Default I/O voltage scale
1262 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1263 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1266 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1267 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1268 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1273 mm->precision = 8; /* For ULAW */
1279 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1282 dbri->mm.data[0] |= 63;
1283 dbri->mm.data[1] |= 63;
1284 dbri->mm.data[2] &= ~15;
1285 dbri->mm.data[3] &= ~15;
1287 /* Start by setting the playback attenuation. */
1288 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1289 int left_gain = info->left_gain & 0x3f;
1290 int right_gain = info->right_gain & 0x3f;
1292 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1293 dbri->mm.data[1] &= ~0x3f;
1294 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1295 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1297 /* Now set the recording gain. */
1298 info = &dbri->stream_info[DBRI_REC];
1299 left_gain = info->left_gain & 0xf;
1300 right_gain = info->right_gain & 0xf;
1301 dbri->mm.data[2] |= CS4215_LG(left_gain);
1302 dbri->mm.data[3] |= CS4215_RG(right_gain);
1305 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1309 * Set the CS4215 to data mode.
1311 static void cs4215_open(struct snd_dbri * dbri)
1316 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1317 dbri->mm.channels, dbri->mm.precision);
1319 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1320 * to make sure this takes. This avoids clicking noises.
1323 cs4215_setdata(dbri, 1);
1328 * Pipe 4: Send timeslots 1-4 (audio data)
1329 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1330 * Pipe 6: Receive timeslots 1-4 (audio data)
1331 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1332 * interrupt, and the rest of the data (slot 5 and 8) is
1333 * not relevant for us (only for doublechecking).
1335 * Just like in control mode, the time slots are all offset by eight
1336 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1337 * even if it's the CHI master. Don't ask me...
1339 tmp = sbus_readl(dbri->regs + REG0);
1340 tmp &= ~(D_C); /* Disable CHI */
1341 sbus_writel(tmp, dbri->regs + REG0);
1343 /* Switch CS4215 to data mode - set PIO3 to 1 */
1344 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1345 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1347 reset_chi(dbri, CHIslave, 128);
1349 /* Note: this next doesn't work for 8-bit stereo, because the two
1350 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1351 * (See CS4215 datasheet Fig 15)
1353 * DBRI non-contiguous mode would be required to make this work.
1355 data_width = dbri->mm.channels * dbri->mm.precision;
1357 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1358 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1359 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1360 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1362 /* FIXME: enable CHI after _setdata? */
1363 tmp = sbus_readl(dbri->regs + REG0);
1364 tmp |= D_C; /* Enable CHI */
1365 sbus_writel(tmp, dbri->regs + REG0);
1367 cs4215_setdata(dbri, 0);
1371 * Send the control information (i.e. audio format)
1373 static int cs4215_setctrl(struct snd_dbri * dbri)
1378 /* FIXME - let the CPU do something useful during these delays */
1380 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1381 * to make sure this takes. This avoids clicking noises.
1383 cs4215_setdata(dbri, 1);
1387 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1388 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1390 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1391 sbus_writel(val, dbri->regs + REG2);
1392 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1395 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1396 * operate as CHI master, supplying clocking and frame synchronization.
1398 * In Data mode, however, the CS4215 must be CHI master to insure
1399 * that its data stream is synchronous with its codec.
1401 * The upshot of all this? We start by putting the DBRI into master
1402 * mode, program the CS4215 in Control mode, then switch the CS4215
1403 * into Data mode and put the DBRI into slave mode. Various timing
1404 * requirements must be observed along the way.
1406 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1407 * others?), the addressing of the CS4215's time slots is
1408 * offset by eight bits, so we add eight to all the "cycle"
1409 * values in the Define Time Slot (DTS) commands. This is
1410 * done in hardware by a TI 248 that delays the DBRI->4215
1411 * frame sync signal by eight clock cycles. Anybody know why?
1413 tmp = sbus_readl(dbri->regs + REG0);
1414 tmp &= ~D_C; /* Disable CHI */
1415 sbus_writel(tmp, dbri->regs + REG0);
1417 reset_chi(dbri, CHImaster, 128);
1421 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1422 * Pipe 18: Receive timeslot 1 (clb).
1423 * Pipe 19: Receive timeslot 7 (version).
1426 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1427 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1428 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1430 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1431 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1432 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1434 tmp = sbus_readl(dbri->regs + REG0);
1435 tmp |= D_C; /* Enable CHI */
1436 sbus_writel(tmp, dbri->regs + REG0);
1438 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1439 msleep_interruptible(1);
1442 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1447 /* Disable changes to our copy of the version number, as we are about
1448 * to leave control mode.
1450 recv_fixed(dbri, 19, NULL);
1452 /* Terminate CS4215 control mode - data sheet says
1453 * "Set CLB=1 and send two more frames of valid control info"
1455 dbri->mm.ctrl[0] |= CS4215_CLB;
1456 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1458 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1461 cs4215_setdata(dbri, 0);
1467 * Setup the codec with the sampling rate, audio format and number of
1469 * As part of the process we resend the settings for the data
1470 * timeslots as well.
1472 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1473 snd_pcm_format_t format, unsigned int channels)
1478 /* Lookup index for this rate */
1479 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1480 if (CS4215_FREQ[freq_idx].freq == rate)
1483 if (CS4215_FREQ[freq_idx].freq != rate) {
1484 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1489 case SNDRV_PCM_FORMAT_MU_LAW:
1490 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1491 dbri->mm.precision = 8;
1493 case SNDRV_PCM_FORMAT_A_LAW:
1494 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1495 dbri->mm.precision = 8;
1497 case SNDRV_PCM_FORMAT_U8:
1498 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1499 dbri->mm.precision = 8;
1501 case SNDRV_PCM_FORMAT_S16_BE:
1502 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1503 dbri->mm.precision = 16;
1506 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1510 /* Add rate parameters */
1511 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1512 dbri->mm.ctrl[2] = CS4215_XCLK |
1513 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1515 dbri->mm.channels = channels;
1516 /* Stereo bit: 8 bit stereo not working yet. */
1517 if ((channels > 1) && (dbri->mm.precision == 16))
1518 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1520 ret = cs4215_setctrl(dbri);
1522 cs4215_open(dbri); /* set codec to data mode */
1530 static int cs4215_init(struct snd_dbri * dbri)
1532 u32 reg2 = sbus_readl(dbri->regs + REG2);
1533 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1535 /* Look for the cs4215 chips */
1536 if (reg2 & D_PIO2) {
1537 dprintk(D_MM, "Onboard CS4215 detected\n");
1538 dbri->mm.onboard = 1;
1540 if (reg2 & D_PIO0) {
1541 dprintk(D_MM, "Speakerbox detected\n");
1542 dbri->mm.onboard = 0;
1544 if (reg2 & D_PIO2) {
1545 printk(KERN_INFO "DBRI: Using speakerbox / "
1546 "ignoring onboard mmcodec.\n");
1547 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1551 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1552 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1556 cs4215_setup_pipes(dbri);
1558 cs4215_init_data(&dbri->mm);
1560 /* Enable capture of the status & version timeslots. */
1561 recv_fixed(dbri, 18, &dbri->mm.status);
1562 recv_fixed(dbri, 19, &dbri->mm.version);
1564 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1565 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1566 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1570 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1576 ****************************************************************************
1577 *************************** DBRI interrupt handler *************************
1578 ****************************************************************************
1580 The DBRI communicates with the CPU mainly via a circular interrupt
1581 buffer. When an interrupt is signaled, the CPU walks through the
1582 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1583 Complicated interrupts are handled by dedicated functions (which
1584 appear first in this file). Any pending interrupts can be serviced by
1585 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1586 interrupts are disabled. This function is used by dbri_cmdlock()
1587 to make sure we're synced up with the chip before each command sequence,
1588 even if we're running cli'ed.
1594 * Transmit the current TD's for recording/playing, if needed.
1595 * For playback, ALSA has filled the DMA memory with new data (we hope).
1597 static void xmit_descs(unsigned long data)
1599 struct snd_dbri *dbri = (struct snd_dbri *) data;
1600 struct dbri_streaminfo *info;
1602 unsigned long flags;
1606 return; /* Disabled */
1608 /* First check the recording stream for buffer overflow */
1609 info = &dbri->stream_info[DBRI_REC];
1610 spin_lock_irqsave(&dbri->lock, flags);
1612 if ((info->left >= info->size) && (info->pipe >= 0)) {
1613 first_td = dbri->pipes[info->pipe].first_desc;
1615 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1617 /* Stream could be closed by the time we run. */
1622 cmd = dbri_cmdlock(dbri, NoGetLock);
1623 *(cmd++) = DBRI_CMD(D_SDP, 0,
1624 dbri->pipes[info->pipe].sdp
1625 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1626 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1627 dbri_cmdsend(dbri, cmd);
1629 /* Reset our admin of the pipe & bytes read. */
1630 dbri->pipes[info->pipe].desc = first_td;
1635 spin_unlock_irqrestore(&dbri->lock, flags);
1637 /* Now check the playback stream for buffer underflow */
1638 info = &dbri->stream_info[DBRI_PLAY];
1639 spin_lock_irqsave(&dbri->lock, flags);
1641 if ((info->left <= 0) && (info->pipe >= 0)) {
1642 first_td = dbri->pipes[info->pipe].first_desc;
1644 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1646 /* Stream could be closed by the time we run. */
1648 spin_unlock_irqrestore(&dbri->lock, flags);
1652 cmd = dbri_cmdlock(dbri, NoGetLock);
1653 *(cmd++) = DBRI_CMD(D_SDP, 0,
1654 dbri->pipes[info->pipe].sdp
1655 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1656 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1657 dbri_cmdsend(dbri, cmd);
1659 /* Reset our admin of the pipe & bytes written. */
1660 dbri->pipes[info->pipe].desc = first_td;
1661 info->left = info->size;
1663 spin_unlock_irqrestore(&dbri->lock, flags);
1666 static DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0);
1668 /* transmission_complete_intr()
1670 * Called by main interrupt handler when DBRI signals transmission complete
1671 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1673 * Walks through the pipe's list of transmit buffer descriptors and marks
1674 * them as available. Stops when the first descriptor is found without
1675 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1677 * The DMA buffers are not released, but re-used. Since the transmit buffer
1678 * descriptors are not clobbered, they can be re-submitted as is. This is
1679 * done by the xmit_descs() tasklet above since that could take longer.
1682 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1684 struct dbri_streaminfo *info;
1689 info = &dbri->stream_info[DBRI_PLAY];
1691 td = dbri->pipes[pipe].desc;
1693 if (td >= DBRI_NO_DESCS) {
1694 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1698 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1699 if (!(status & DBRI_TD_TBC)) {
1703 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1705 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1706 len = DBRI_RD_CNT(dbri->dma->desc[td].word1);
1707 info->offset += len;
1710 /* On the last TD, transmit them all again. */
1711 if (dbri->next_desc[td] == -1) {
1712 if (info->left > 0) {
1714 "%d bytes left after last transfer.\n",
1718 tasklet_schedule(&xmit_descs_task);
1721 td = dbri->next_desc[td];
1722 dbri->pipes[pipe].desc = td;
1726 if (spin_is_locked(&dbri->lock)) {
1727 spin_unlock(&dbri->lock);
1728 snd_pcm_period_elapsed(info->substream);
1729 spin_lock(&dbri->lock);
1731 snd_pcm_period_elapsed(info->substream);
1734 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1736 struct dbri_streaminfo *info;
1737 int rd = dbri->pipes[pipe].desc;
1740 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1741 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1745 dbri->dma->desc[rd].ba = 0;
1746 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1747 status = dbri->dma->desc[rd].word1;
1748 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1750 info = &dbri->stream_info[DBRI_REC];
1751 info->offset += DBRI_RD_CNT(status);
1752 info->left += DBRI_RD_CNT(status);
1754 /* FIXME: Check status */
1756 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1757 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1759 /* On the last TD, transmit them all again. */
1760 if (dbri->next_desc[rd] == -1) {
1761 if (info->left > info->size) {
1763 "%d bytes recorded in %d size buffer.\n",
1764 info->left, info->size);
1766 tasklet_schedule(&xmit_descs_task);
1770 if (spin_is_locked(&dbri->lock)) {
1771 spin_unlock(&dbri->lock);
1772 snd_pcm_period_elapsed(info->substream);
1773 spin_lock(&dbri->lock);
1775 snd_pcm_period_elapsed(info->substream);
1778 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1780 int val = D_INTR_GETVAL(x);
1781 int channel = D_INTR_GETCHAN(x);
1782 int command = D_INTR_GETCMD(x);
1783 int code = D_INTR_GETCODE(x);
1785 int rval = D_INTR_GETRVAL(x);
1788 if (channel == D_INTR_CMD) {
1789 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1790 cmds[command], val);
1792 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1793 channel, code, rval);
1796 if (channel == D_INTR_CMD && command == D_WAIT) {
1797 dbri->wait_ackd = val;
1798 if (dbri->wait_send != val) {
1799 printk(KERN_ERR "Processing wait command %d when %d was send.\n",
1800 val, dbri->wait_send);
1807 reception_complete_intr(dbri, channel);
1811 transmission_complete_intr(dbri, channel);
1814 /* UNDR - Transmission underrun
1815 * resend SDP command with clear pipe bit (C) set
1821 int td = dbri->pipes[pipe].desc;
1823 dbri->dma->desc[td].word4 = 0;
1824 cmd = dbri_cmdlock(dbri, NoGetLock);
1825 *(cmd++) = DBRI_CMD(D_SDP, 0,
1826 dbri->pipes[pipe].sdp
1827 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1828 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1829 dbri_cmdsend(dbri, cmd);
1833 /* FXDT - Fixed data change */
1834 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1835 val = reverse_bytes(val, dbri->pipes[channel].length);
1837 if (dbri->pipes[channel].recv_fixed_ptr)
1838 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1841 if (channel != D_INTR_CMD)
1843 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1847 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1848 * buffer until it finds a zero word (indicating nothing more to do
1849 * right now). Non-zero words require processing and are handed off
1850 * to dbri_process_one_interrupt AFTER advancing the pointer. This
1851 * order is important since we might recurse back into this function
1852 * and need to make sure the pointer has been advanced first.
1854 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1858 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1859 dbri->dma->intr[dbri->dbri_irqp] = 0;
1861 if (dbri->dbri_irqp == DBRI_INT_BLK)
1862 dbri->dbri_irqp = 1;
1864 dbri_process_one_interrupt(dbri, x);
1868 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1869 struct pt_regs *regs)
1871 struct snd_dbri *dbri = dev_id;
1872 static int errcnt = 0;
1877 spin_lock(&dbri->lock);
1880 * Read it, so the interrupt goes away.
1882 x = sbus_readl(dbri->regs + REG1);
1884 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1889 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1893 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1897 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1900 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1902 /* Some of these SBus errors cause the chip's SBus circuitry
1903 * to be disabled, so just re-enable and try to keep going.
1905 * The only one I've seen is MRR, which will be triggered
1906 * if you let a transmit pipe underrun, then try to CDP it.
1908 * If these things persist, we reset the chip.
1910 if ((++errcnt) % 10 == 0) {
1911 dprintk(D_INT, "Interrupt errors exceeded.\n");
1914 tmp = sbus_readl(dbri->regs + REG0);
1916 sbus_writel(tmp, dbri->regs + REG0);
1920 dbri_process_interrupt_buffer(dbri);
1922 /* FIXME: Write 0 into regs to ACK interrupt */
1924 spin_unlock(&dbri->lock);
1929 /****************************************************************************
1931 ****************************************************************************/
1932 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1933 .info = (SNDRV_PCM_INFO_MMAP |
1934 SNDRV_PCM_INFO_INTERLEAVED |
1935 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1936 SNDRV_PCM_INFO_MMAP_VALID),
1937 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1938 SNDRV_PCM_FMTBIT_A_LAW |
1939 SNDRV_PCM_FMTBIT_U8 |
1940 SNDRV_PCM_FMTBIT_S16_BE,
1941 .rates = SNDRV_PCM_RATE_8000_48000,
1946 .buffer_bytes_max = (64 * 1024),
1947 .period_bytes_min = 1,
1948 .period_bytes_max = DBRI_TD_MAXCNT,
1950 .periods_max = 1024,
1953 static int snd_dbri_open(struct snd_pcm_substream *substream)
1955 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1956 struct snd_pcm_runtime *runtime = substream->runtime;
1957 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1958 unsigned long flags;
1960 dprintk(D_USR, "open audio output.\n");
1961 runtime->hw = snd_dbri_pcm_hw;
1963 spin_lock_irqsave(&dbri->lock, flags);
1964 info->substream = substream;
1967 info->dvma_buffer = 0;
1969 spin_unlock_irqrestore(&dbri->lock, flags);
1976 static int snd_dbri_close(struct snd_pcm_substream *substream)
1978 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1979 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1981 dprintk(D_USR, "close audio output.\n");
1982 info->substream = NULL;
1989 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
1990 struct snd_pcm_hw_params *hw_params)
1992 struct snd_pcm_runtime *runtime = substream->runtime;
1993 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1994 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1998 /* set sampling rate, audio format and number of channels */
1999 ret = cs4215_prepare(dbri, params_rate(hw_params),
2000 params_format(hw_params),
2001 params_channels(hw_params));
2005 if ((ret = snd_pcm_lib_malloc_pages(substream,
2006 params_buffer_bytes(hw_params))) < 0) {
2007 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2011 /* hw_params can get called multiple times. Only map the DMA once.
2013 if (info->dvma_buffer == 0) {
2014 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2015 direction = SBUS_DMA_TODEVICE;
2017 direction = SBUS_DMA_FROMDEVICE;
2019 info->dvma_buffer = sbus_map_single(dbri->sdev,
2021 params_buffer_bytes(hw_params),
2025 direction = params_buffer_bytes(hw_params);
2026 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2027 direction, info->dvma_buffer);
2031 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2033 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2034 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2036 dprintk(D_USR, "hw_free.\n");
2038 /* hw_free can get called multiple times. Only unmap the DMA once.
2040 if (info->dvma_buffer) {
2041 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2042 direction = SBUS_DMA_TODEVICE;
2044 direction = SBUS_DMA_FROMDEVICE;
2046 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2047 substream->runtime->buffer_size, direction);
2048 info->dvma_buffer = 0;
2052 return snd_pcm_lib_free_pages(substream);
2055 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2057 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2058 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2059 struct snd_pcm_runtime *runtime = substream->runtime;
2062 info->size = snd_pcm_lib_buffer_bytes(substream);
2063 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2064 info->pipe = 4; /* Send pipe */
2066 info->pipe = 6; /* Receive pipe */
2067 info->left = info->size; /* To trigger submittal */
2070 spin_lock_irq(&dbri->lock);
2072 /* Setup the all the transmit/receive desciptors to cover the
2075 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2076 snd_pcm_lib_period_bytes(substream));
2078 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
2080 spin_unlock_irq(&dbri->lock);
2082 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2086 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2088 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2089 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2093 case SNDRV_PCM_TRIGGER_START:
2094 dprintk(D_USR, "start audio, period is %d bytes\n",
2095 (int)snd_pcm_lib_period_bytes(substream));
2096 /* Enable & schedule the tasklet that re-submits the TDs. */
2097 xmit_descs_task.data = (unsigned long)dbri;
2098 tasklet_schedule(&xmit_descs_task);
2100 case SNDRV_PCM_TRIGGER_STOP:
2101 dprintk(D_USR, "stop audio.\n");
2102 /* Make the tasklet bail out immediately. */
2103 xmit_descs_task.data = 0;
2104 reset_pipe(dbri, info->pipe);
2113 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2115 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2116 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2117 snd_pcm_uframes_t ret;
2119 ret = bytes_to_frames(substream->runtime, info->offset)
2120 % substream->runtime->buffer_size;
2121 dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n",
2126 static struct snd_pcm_ops snd_dbri_ops = {
2127 .open = snd_dbri_open,
2128 .close = snd_dbri_close,
2129 .ioctl = snd_pcm_lib_ioctl,
2130 .hw_params = snd_dbri_hw_params,
2131 .hw_free = snd_dbri_hw_free,
2132 .prepare = snd_dbri_prepare,
2133 .trigger = snd_dbri_trigger,
2134 .pointer = snd_dbri_pointer,
2137 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2139 struct snd_pcm *pcm;
2142 if ((err = snd_pcm_new(dbri->card,
2143 /* ID */ "sun_dbri",
2145 /* playback count */ 1,
2146 /* capture count */ 1, &pcm)) < 0)
2148 snd_assert(pcm != NULL, return -EINVAL);
2150 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2151 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2153 pcm->private_data = dbri;
2154 pcm->info_flags = 0;
2155 strcpy(pcm->name, dbri->card->shortname);
2157 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2158 SNDRV_DMA_TYPE_CONTINUOUS,
2159 snd_dma_continuous_data(GFP_KERNEL),
2160 64 * 1024, 64 * 1024)) < 0) {
2167 /*****************************************************************************
2169 *****************************************************************************/
2171 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2172 struct snd_ctl_elem_info *uinfo)
2174 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2176 uinfo->value.integer.min = 0;
2177 if (kcontrol->private_value == DBRI_PLAY) {
2178 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2180 uinfo->value.integer.max = DBRI_MAX_GAIN;
2185 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2186 struct snd_ctl_elem_value *ucontrol)
2188 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2189 struct dbri_streaminfo *info;
2190 snd_assert(dbri != NULL, return -EINVAL);
2191 info = &dbri->stream_info[kcontrol->private_value];
2192 snd_assert(info != NULL, return -EINVAL);
2194 ucontrol->value.integer.value[0] = info->left_gain;
2195 ucontrol->value.integer.value[1] = info->right_gain;
2199 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2200 struct snd_ctl_elem_value *ucontrol)
2202 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2203 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2204 unsigned long flags;
2207 if (info->left_gain != ucontrol->value.integer.value[0]) {
2208 info->left_gain = ucontrol->value.integer.value[0];
2211 if (info->right_gain != ucontrol->value.integer.value[1]) {
2212 info->right_gain = ucontrol->value.integer.value[1];
2216 /* First mute outputs, and wait 1/8000 sec (125 us)
2217 * to make sure this takes. This avoids clicking noises.
2219 spin_lock_irqsave(&dbri->lock, flags);
2221 cs4215_setdata(dbri, 1);
2223 cs4215_setdata(dbri, 0);
2225 spin_unlock_irqrestore(&dbri->lock, flags);
2230 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2231 struct snd_ctl_elem_info *uinfo)
2233 int mask = (kcontrol->private_value >> 16) & 0xff;
2235 uinfo->type = (mask == 1) ?
2236 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2238 uinfo->value.integer.min = 0;
2239 uinfo->value.integer.max = mask;
2243 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2246 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2247 int elem = kcontrol->private_value & 0xff;
2248 int shift = (kcontrol->private_value >> 8) & 0xff;
2249 int mask = (kcontrol->private_value >> 16) & 0xff;
2250 int invert = (kcontrol->private_value >> 24) & 1;
2251 snd_assert(dbri != NULL, return -EINVAL);
2254 ucontrol->value.integer.value[0] =
2255 (dbri->mm.data[elem] >> shift) & mask;
2257 ucontrol->value.integer.value[0] =
2258 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2262 ucontrol->value.integer.value[0] =
2263 mask - ucontrol->value.integer.value[0];
2268 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2269 struct snd_ctl_elem_value *ucontrol)
2271 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2272 unsigned long flags;
2273 int elem = kcontrol->private_value & 0xff;
2274 int shift = (kcontrol->private_value >> 8) & 0xff;
2275 int mask = (kcontrol->private_value >> 16) & 0xff;
2276 int invert = (kcontrol->private_value >> 24) & 1;
2279 snd_assert(dbri != NULL, return -EINVAL);
2281 val = (ucontrol->value.integer.value[0] & mask);
2287 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2288 ~(mask << shift)) | val;
2289 changed = (val != dbri->mm.data[elem]);
2291 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2292 ~(mask << shift)) | val;
2293 changed = (val != dbri->mm.ctrl[elem - 4]);
2296 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2297 "mixer-value=%ld, mm-value=0x%x\n",
2298 mask, changed, ucontrol->value.integer.value[0],
2299 dbri->mm.data[elem & 3]);
2302 /* First mute outputs, and wait 1/8000 sec (125 us)
2303 * to make sure this takes. This avoids clicking noises.
2305 spin_lock_irqsave(&dbri->lock, flags);
2307 cs4215_setdata(dbri, 1);
2309 cs4215_setdata(dbri, 0);
2311 spin_unlock_irqrestore(&dbri->lock, flags);
2316 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2317 timeslots. Shift is the bit offset in the timeslot, mask defines the
2318 number of bits. invert is a boolean for use with attenuation.
2320 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2321 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2322 .info = snd_cs4215_info_single, \
2323 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2324 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2326 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2328 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2329 .name = "Playback Volume",
2330 .info = snd_cs4215_info_volume,
2331 .get = snd_cs4215_get_volume,
2332 .put = snd_cs4215_put_volume,
2333 .private_value = DBRI_PLAY,
2335 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2336 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2337 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2339 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2340 .name = "Capture Volume",
2341 .info = snd_cs4215_info_volume,
2342 .get = snd_cs4215_get_volume,
2343 .put = snd_cs4215_put_volume,
2344 .private_value = DBRI_REC,
2346 /* FIXME: mic/line switch */
2347 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2348 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2349 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2350 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2353 #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
2355 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2357 struct snd_card *card;
2360 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2363 strcpy(card->mixername, card->shortname);
2365 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2366 if ((err = snd_ctl_add(card,
2367 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2371 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2372 dbri->stream_info[idx].left_gain = 0;
2373 dbri->stream_info[idx].right_gain = 0;
2379 /****************************************************************************
2381 ****************************************************************************/
2382 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2384 struct snd_dbri *dbri = entry->private_data;
2386 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2387 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2388 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2389 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2393 static void dbri_debug_read(struct snd_info_entry * entry,
2394 struct snd_info_buffer *buffer)
2396 struct snd_dbri *dbri = entry->private_data;
2398 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2400 for (pipe = 0; pipe < 32; pipe++) {
2401 if (pipe_active(dbri, pipe)) {
2402 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2404 "Pipe %d: %s SDP=0x%x desc=%d, "
2407 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2408 pptr->sdp, pptr->desc,
2409 pptr->length, pptr->nextpipe);
2415 void snd_dbri_proc(struct snd_dbri * dbri)
2417 struct snd_info_entry *entry;
2419 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2420 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2423 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2424 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2425 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2431 ****************************************************************************
2432 **************************** Initialization ********************************
2433 ****************************************************************************
2435 static void snd_dbri_free(struct snd_dbri * dbri);
2437 static int __init snd_dbri_create(struct snd_card *card,
2438 struct sbus_dev *sdev,
2439 struct linux_prom_irqs *irq, int dev)
2441 struct snd_dbri *dbri = card->private_data;
2444 spin_lock_init(&dbri->lock);
2447 dbri->irq = irq->pri;
2449 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2451 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2453 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2454 dbri->dma, dbri->dma_dvma);
2456 /* Map the registers into memory. */
2457 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2458 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2459 dbri->regs_size, "DBRI Registers");
2461 printk(KERN_ERR "DBRI: could not allocate registers\n");
2462 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2463 (void *)dbri->dma, dbri->dma_dvma);
2467 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2468 "DBRI audio", dbri);
2470 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2471 sbus_iounmap(dbri->regs, dbri->regs_size);
2472 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2473 (void *)dbri->dma, dbri->dma_dvma);
2477 /* Do low level initialization of the DBRI and CS4215 chips */
2478 dbri_initialize(dbri);
2479 err = cs4215_init(dbri);
2481 snd_dbri_free(dbri);
2485 dbri->next = dbri_list;
2491 static void snd_dbri_free(struct snd_dbri * dbri)
2493 dprintk(D_GEN, "snd_dbri_free\n");
2497 free_irq(dbri->irq, dbri);
2500 sbus_iounmap(dbri->regs, dbri->regs_size);
2503 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2504 (void *)dbri->dma, dbri->dma_dvma);
2507 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2509 struct snd_dbri *dbri;
2510 struct linux_prom_irqs irq;
2511 struct resource *rp;
2512 struct snd_card *card;
2516 if (sdev->prom_name[9] < 'e') {
2517 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2518 sdev->prom_name[9]);
2522 if (dev >= SNDRV_CARDS)
2529 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2531 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2535 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2536 sizeof(struct snd_dbri));
2540 strcpy(card->driver, "DBRI");
2541 strcpy(card->shortname, "Sun DBRI");
2542 rp = &sdev->resource[0];
2543 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2545 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2547 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2548 snd_card_free(card);
2552 dbri = card->private_data;
2553 if ((err = snd_dbri_pcm(dbri)) < 0)
2556 if ((err = snd_dbri_mixer(dbri)) < 0)
2559 /* /proc file handling */
2560 snd_dbri_proc(dbri);
2562 if ((err = snd_card_register(card)) < 0)
2565 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2567 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2573 snd_dbri_free(dbri);
2574 snd_card_free(card);
2578 /* Probe for the dbri chip and then attach the driver. */
2579 static int __init dbri_init(void)
2581 struct sbus_bus *sbus;
2582 struct sbus_dev *sdev;
2585 /* Probe each SBUS for the DBRI chip(s). */
2586 for_all_sbusdev(sdev, sbus) {
2588 * The version is coded in the last character
2590 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2591 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2592 sdev->prom_name, sdev->slot);
2594 if (dbri_attach(sdev->prom_node, sdev) == 0)
2599 return (found > 0) ? 0 : -EIO;
2602 static void __exit dbri_exit(void)
2604 struct snd_dbri *this = dbri_list;
2606 while (this != NULL) {
2607 struct snd_dbri *next = this->next;
2608 struct snd_card *card = this->card;
2610 snd_dbri_free(this);
2611 snd_card_free(card);
2617 module_init(dbri_init);
2618 module_exit(dbri_exit);