2 * at91rm9200-i2s.c -- ALSA Soc Audio Layer Platform driver and DMA engine
4 * Author: Frank Mandarino <fmandarino@endrelia.com>
5 * Endrelia Technologies Inc.
7 * Based on pxa2xx Platform drivers by
8 * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 * 3rd Mar 2006 Initial version.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <sound/driver.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
31 #include <asm/arch/at91rm9200.h>
32 #include <asm/arch/at91rm9200_ssc.h>
33 #include <asm/arch/at91rm9200_pdc.h>
34 #include <asm/arch/hardware.h>
36 #include "at91rm9200-pcm.h"
39 #define DBG(x...) printk(KERN_DEBUG "at91rm9200-i2s:" x)
44 #define AT91RM9200_I2S_DAIFMT \
45 (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_NF)
47 #define AT91RM9200_I2S_DIR \
48 (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
50 /* priv is (SSC_CMR.DIV << 16 | SSC_TCMR.PERIOD ) */
51 static struct snd_soc_dai_mode at91rm9200_i2s[] = {
53 /* 8k: BCLK = (MCLK/10) = (60MHz/50) = 1.2MHz */
55 .fmt = AT91RM9200_I2S_DAIFMT,
56 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
57 .pcmrate = SNDRV_PCM_RATE_8000,
58 .pcmdir = AT91RM9200_I2S_DIR,
59 .flags = SND_SOC_DAI_BFS_DIV,
61 .bfs = SND_SOC_FSBD(10),
62 .priv = (25 << 16 | 74),
65 /* 16k: BCLK = (MCLK/3) ~= (60MHz/14) = 4.285714MHz */
67 .fmt = AT91RM9200_I2S_DAIFMT,
68 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
69 .pcmrate = SNDRV_PCM_RATE_16000,
70 .pcmdir = AT91RM9200_I2S_DIR,
71 .flags = SND_SOC_DAI_BFS_DIV,
73 .bfs = SND_SOC_FSBD(3),
74 .priv = (7 << 16 | 133),
77 /* 32k: BCLK = (MCLK/3) ~= (60MHz/14) = 4.285714MHz */
79 .fmt = AT91RM9200_I2S_DAIFMT,
80 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
81 .pcmrate = SNDRV_PCM_RATE_32000,
82 .pcmdir = AT91RM9200_I2S_DIR,
83 .flags = SND_SOC_DAI_BFS_DIV,
85 .bfs = SND_SOC_FSBD(3),
86 .priv = (7 << 16 | 66),
89 /* 48k: BCLK = (MCLK/5) ~= (60MHz/26) = 2.3076923MHz */
91 .fmt = AT91RM9200_I2S_DAIFMT,
92 .pcmfmt = SNDRV_PCM_FMTBIT_S16_LE,
93 .pcmrate = SNDRV_PCM_RATE_48000,
94 .pcmdir = AT91RM9200_I2S_DIR,
95 .flags = SND_SOC_DAI_BFS_DIV,
98 .priv = (13 << 16 | 23),
104 * SSC registers required by the PCM DMA engine.
106 static struct at91rm9200_ssc_regs ssc_reg[3] = {
108 .cr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_SSC_CR),
109 .ier = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_SSC_IER),
110 .idr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_SSC_IDR),
113 .cr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_SSC_CR),
114 .ier = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_SSC_IER),
115 .idr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_SSC_IDR),
118 .cr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_SSC_CR),
119 .ier = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_SSC_IER),
120 .idr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_SSC_IDR),
124 static struct at91rm9200_pdc_regs pdc_tx_reg[3] = {
126 .xpr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_TPR),
127 .xcr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_TCR),
128 .xnpr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_TNPR),
129 .xncr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_TNCR),
130 .ptcr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_PTCR),
133 .xpr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_TPR),
134 .xcr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_TCR),
135 .xnpr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_TNPR),
136 .xncr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_TNCR),
137 .ptcr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_PTCR),
140 .xpr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_TPR),
141 .xcr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_TCR),
142 .xnpr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_TNPR),
143 .xncr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_TNCR),
144 .ptcr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_PTCR),
148 static struct at91rm9200_pdc_regs pdc_rx_reg[3] = {
150 .xpr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_RPR),
151 .xcr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_RCR),
152 .xnpr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_RNPR),
153 .xncr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_RNCR),
154 .ptcr = (void __iomem *) (AT91_VA_BASE_SSC0 + AT91_PDC_PTCR),
157 .xpr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_RPR),
158 .xcr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_RCR),
159 .xnpr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_RNPR),
160 .xncr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_RNCR),
161 .ptcr = (void __iomem *) (AT91_VA_BASE_SSC1 + AT91_PDC_PTCR),
164 .xpr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_RPR),
165 .xcr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_RCR),
166 .xnpr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_RNPR),
167 .xncr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_RNCR),
168 .ptcr = (void __iomem *) (AT91_VA_BASE_SSC2 + AT91_PDC_PTCR),
173 * SSC & PDC status bits for transmit and receive.
175 static struct at91rm9200_ssc_mask ssc_tx_mask = {
176 .ssc_enable = AT91_SSC_TXEN,
177 .ssc_disable = AT91_SSC_TXDIS,
178 .ssc_endx = AT91_SSC_ENDTX,
179 .ssc_endbuf = AT91_SSC_TXBUFE,
180 .pdc_enable = AT91_PDC_TXTEN,
181 .pdc_disable = AT91_PDC_TXTDIS,
184 static struct at91rm9200_ssc_mask ssc_rx_mask = {
185 .ssc_enable = AT91_SSC_RXEN,
186 .ssc_disable = AT91_SSC_RXDIS,
187 .ssc_endx = AT91_SSC_ENDRX,
188 .ssc_endbuf = AT91_SSC_RXBUFF,
189 .pdc_enable = AT91_PDC_RXTEN,
190 .pdc_disable = AT91_PDC_RXTDIS,
194 * A MUTEX is used to protect an SSC initialzed flag which allows
195 * the substream hw_params() call to initialize the SSC only if
196 * there are no other substreams open. If there are other
197 * substreams open, the hw_param() call can only check that
198 * it is using the same format and rate.
200 static DECLARE_MUTEX(ssc0_mutex);
201 static DECLARE_MUTEX(ssc1_mutex);
202 static DECLARE_MUTEX(ssc2_mutex);
207 static at91rm9200_pcm_dma_params_t ssc_dma_params[3][2] = {
209 .name = "SSC0/I2S PCM Stereo out",
211 .pdc = &pdc_tx_reg[0],
212 .mask = &ssc_tx_mask,
215 .name = "SSC0/I2S PCM Stereo in",
217 .pdc = &pdc_rx_reg[0],
218 .mask = &ssc_rx_mask,
221 .name = "SSC1/I2S PCM Stereo out",
223 .pdc = &pdc_tx_reg[1],
224 .mask = &ssc_tx_mask,
227 .name = "SSC1/I2S PCM Stereo in",
229 .pdc = &pdc_rx_reg[1],
230 .mask = &ssc_rx_mask,
233 .name = "SSC2/I2S PCM Stereo out",
235 .pdc = &pdc_tx_reg[2],
236 .mask = &ssc_tx_mask,
239 .name = "SSC1/I2S PCM Stereo in",
241 .pdc = &pdc_rx_reg[2],
242 .mask = &ssc_rx_mask,
247 struct at91rm9200_ssc_state {
257 static struct at91rm9200_ssc_info {
259 void __iomem *ssc_base;
261 spinlock_t lock; /* lock for dir_mask */
262 int dir_mask; /* 0=unused, 1=playback, 2=capture */
263 struct semaphore *mutex;
267 at91rm9200_pcm_dma_params_t *dma_params[2];
268 struct at91rm9200_ssc_state ssc_state;
273 .ssc_base = (void __iomem *) AT91_VA_BASE_SSC0,
275 .lock = SPIN_LOCK_UNLOCKED,
277 .mutex = &ssc0_mutex,
282 .ssc_base = (void __iomem *) AT91_VA_BASE_SSC1,
284 .lock = SPIN_LOCK_UNLOCKED,
286 .mutex = &ssc1_mutex,
291 .ssc_base = (void __iomem *) AT91_VA_BASE_SSC2,
293 .lock = SPIN_LOCK_UNLOCKED,
295 .mutex = &ssc2_mutex,
301 static irqreturn_t at91rm9200_i2s_interrupt(int irq, void *dev_id)
303 struct at91rm9200_ssc_info *ssc_p = dev_id;
304 at91rm9200_pcm_dma_params_t *dma_params;
308 ssc_sr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_SR)
309 & at91_ssc_read(ssc_p->ssc_base + AT91_SSC_IMR);
312 * Loop through the substreams attached to this SSC. If
313 * a DMA-related interrupt occurred on that substream, call
314 * the DMA interrupt handler function, if one has been
315 * registered in the dma_params structure by the PCM driver.
317 for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
318 dma_params = ssc_p->dma_params[i];
320 if (dma_params != NULL && dma_params->dma_intr_handler != NULL &&
322 (dma_params->mask->ssc_endx | dma_params->mask->ssc_endbuf)))
324 dma_params->dma_intr_handler(ssc_sr, dma_params->substream);
330 static int at91rm9200_i2s_startup(struct snd_pcm_substream *substream)
332 struct snd_soc_pcm_runtime *rtd = substream->private_data;
333 struct at91rm9200_ssc_info *ssc_p = &ssc_info[rtd->cpu_dai->id];
336 DBG("i2s_startup: SSC_SR=0x%08lx\n",
337 at91_ssc_read(ssc_p->ssc_base + AT91_SSC_SR));
338 dir_mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0x1 : 0x2;
340 spin_lock_irq(&ssc_p->lock);
341 if (ssc_p->dir_mask & dir_mask) {
342 spin_unlock_irq(&ssc_p->lock);
345 ssc_p->dir_mask |= dir_mask;
346 spin_unlock_irq(&ssc_p->lock);
351 static void at91rm9200_i2s_shutdown(struct snd_pcm_substream *substream)
353 struct snd_soc_pcm_runtime *rtd = substream->private_data;
354 struct at91rm9200_ssc_info *ssc_p = &ssc_info[rtd->cpu_dai->id];
355 at91rm9200_pcm_dma_params_t *dma_params = rtd->cpu_dai->dma_data;
358 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
360 if (dma_params != NULL) {
361 at91_ssc_write(dma_params->ssc->cr, dma_params->mask->ssc_disable);
362 DBG("%s disabled SSC_SR=0x%08lx\n", (dir ? "receive" : "transmit"),
363 at91_ssc_read(ssc_p->ssc_base + AT91_SSC_SR));
365 dma_params->substream = NULL;
366 ssc_p->dma_params[dir] = NULL;
371 spin_lock_irq(&ssc_p->lock);
372 ssc_p->dir_mask &= ~dir_mask;
373 if (!ssc_p->dir_mask) {
374 /* Shutdown the SSC clock. */
375 DBG("Stopping pid %d clock\n", ssc_p->pid);
376 at91_sys_write(AT91_PMC_PCDR, ssc_p->pid);
378 if (ssc_p->initialized)
379 free_irq(ssc_p->pid, ssc_p);
382 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_CR, AT91_SSC_SWRST);
384 /* Force a re-init on the next hw_params() call. */
385 ssc_p->initialized = 0;
387 spin_unlock_irq(&ssc_p->lock);
391 static int at91rm9200_i2s_suspend(struct platform_device *pdev,
392 struct snd_soc_cpu_dai *dai)
394 struct at91rm9200_ssc_info *ssc_p;
399 ssc_p = &ssc_info[dai->id];
401 /* Save the status register before disabling transmit and receive. */
402 ssc_p->state->ssc_sr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_SR);
403 at91_ssc_write(ssc_p->ssc_base +
404 AT91_SSC_CR, AT91_SSC_TXDIS | AT91_SSC_RXDIS);
406 /* Save the current interrupt mask, then disable unmasked interrupts. */
407 ssc_p->state->ssc_imr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_IMR);
408 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_IDR, ssc_p->state->ssc_imr);
410 ssc_p->state->ssc_cmr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_CMR);
411 ssc_p->state->ssc_rcmr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_RCMR);
412 ssc_p->state->ssc_rfmr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_RCMR);
413 ssc_p->state->ssc_tcmr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_RCMR);
414 ssc_p->state->ssc_tfmr = at91_ssc_read(ssc_p->ssc_base + AT91_SSC_RCMR);
419 static int at91rm9200_i2s_resume(struct platform_device *pdev,
420 struct snd_soc_cpu_dai *dai)
422 struct at91rm9200_ssc_info *ssc_p;
428 ssc_p = &ssc_info[dai->id];
430 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_RCMR, ssc_p->state->ssc_tfmr);
431 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_RCMR, ssc_p->state->ssc_tcmr);
432 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_RCMR, ssc_p->state->ssc_rfmr);
433 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_RCMR, ssc_p->state->ssc_rcmr);
434 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_CMR, ssc_p->state->ssc_cmr);
436 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_IER, ssc_p->state->ssc_imr);
438 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_CR,
439 ((ssc_p->state->ssc_sr & AT91_SSC_RXENA) ? AT91_SSC_RXEN : 0) |
440 ((ssc_p->state->ssc_sr & AT91_SSC_TXENA) ? AT91_SSC_TXEN : 0));
446 #define at91rm9200_i2s_suspend NULL
447 #define at91rm9200_i2s_resume NULL
450 static unsigned int at91rm9200_i2s_config_sysclk(
451 struct snd_soc_cpu_dai *iface, struct snd_soc_clock_info *info,
454 /* Currently, there is only support for USB (12Mhz) mode */
460 static int at91rm9200_i2s_hw_params(struct snd_pcm_substream *substream,
461 struct snd_pcm_hw_params *params)
463 struct snd_soc_pcm_runtime *rtd = substream->private_data;
464 int id = rtd->cpu_dai->id;
465 struct at91rm9200_ssc_info *ssc_p = &ssc_info[id];
466 at91rm9200_pcm_dma_params_t *dma_params;
467 unsigned int pcmfmt, rate;
468 int dir, channels, bits;
471 u32 div, period, tfmr, rfmr, tcmr, rcmr;
475 * Currently, there is only one set of dma params for
476 * each direction. If more are added, this code will
477 * have to be changed to select the proper set.
479 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
481 dma_params = &ssc_dma_params[id][dir];
482 dma_params->substream = substream;
484 ssc_p->dma_params[dir] = dma_params;
485 rtd->cpu_dai->dma_data = dma_params;
487 rate = params_rate(params);
488 channels = params_channels(params);
490 pcmfmt = rtd->cpu_dai->dai_runtime.pcmfmt;
492 case SNDRV_PCM_FMTBIT_S16_LE:
493 /* likely this is all we'll ever support, but ... */
495 dma_params->pdc_xfer_size = 2;
498 printk(KERN_WARNING "at91rm9200-i2s: unsupported format %x\n",
503 /* Don't allow both SSC substreams to initialize at the same time. */
507 * If this SSC is alreadly initialized, then this substream must use
508 * the same format and rate.
510 if (ssc_p->initialized) {
511 if (pcmfmt != ssc_p->pcmfmt || rate != ssc_p->rate) {
512 printk(KERN_WARNING "at91rm9200-i2s: "
513 "incompatible substream in other direction\n");
518 /* Enable PMC peripheral clock for this SSC */
519 DBG("Starting pid %d clock\n", ssc_p->pid);
520 at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->pid);
523 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_CR, AT91_SSC_SWRST);
525 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_RPR, 0);
526 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_RCR, 0);
527 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_RNPR, 0);
528 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_RNCR, 0);
529 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_TPR, 0);
530 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_TCR, 0);
531 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_TNPR, 0);
532 at91_ssc_write(ssc_p->ssc_base + AT91_PDC_TNCR, 0);
534 mck_clk = clk_get(NULL, "mck");
536 div = rtd->cpu_dai->dai_runtime.priv >> 16;
537 period = rtd->cpu_dai->dai_runtime.priv & 0xffff;
538 bclk = 60000000 / (2 * div);
540 DBG("mck %ld fsbd %d bfs %d bfs_real %d bclk %ld div %d period %d\n",
541 clk_get_rate(mck_clk),
543 rtd->cpu_dai->dai_runtime.bfs,
544 SND_SOC_FSBD_REAL(rtd->cpu_dai->dai_runtime.bfs),
551 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_CMR, div);
554 * Setup the TFMR and RFMR for the proper data format.
557 (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
558 | (( 0 << 23) & AT91_SSC_FSDEN)
559 | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
560 | (((bits - 1) << 16) & AT91_SSC_FSLEN)
561 | (((channels - 1) << 8) & AT91_SSC_DATNB)
562 | (( 1 << 7) & AT91_SSC_MSBF)
563 | (( 0 << 5) & AT91_SSC_DATDEF)
564 | (((bits - 1) << 0) & AT91_SSC_DATALEN);
565 DBG("SSC_TFMR=0x%08x\n", tfmr);
566 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_TFMR, tfmr);
569 (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
570 | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
571 | (( 0 << 16) & AT91_SSC_FSLEN)
572 | (((channels - 1) << 8) & AT91_SSC_DATNB)
573 | (( 1 << 7) & AT91_SSC_MSBF)
574 | (( 0 << 5) & AT91_SSC_LOOP)
575 | (((bits - 1) << 0) & AT91_SSC_DATALEN);
577 DBG("SSC_RFMR=0x%08x\n", rfmr);
578 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_RFMR, rfmr);
581 * Setup the TCMR and RCMR to generate the proper BCLK
585 (( period << 24) & AT91_SSC_PERIOD)
586 | (( 1 << 16) & AT91_SSC_STTDLY)
587 | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
588 | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
589 | (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO)
590 | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
592 DBG("SSC_TCMR=0x%08x\n", tcmr);
593 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_TCMR, tcmr);
596 (( 0 << 24) & AT91_SSC_PERIOD)
597 | (( 1 << 16) & AT91_SSC_STTDLY)
598 | (( AT91_SSC_START_TX_RX ) & AT91_SSC_START)
599 | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
600 | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
601 | (( AT91_SSC_CKS_CLOCK ) & AT91_SSC_CKS);
603 DBG("SSC_RCMR=0x%08x\n", rcmr);
604 at91_ssc_write(ssc_p->ssc_base + AT91_SSC_RCMR, rcmr);
606 if ((ret = request_irq(ssc_p->pid, at91rm9200_i2s_interrupt,
607 0, ssc_p->name, ssc_p)) < 0) {
608 printk(KERN_WARNING "at91rm9200-i2s: request_irq failure\n");
613 * Save the current substream parameters in order to check
614 * that the substream in the opposite direction uses the
617 ssc_p->pcmfmt = pcmfmt;
619 ssc_p->initialized = 1;
621 DBG("hw_params: SSC initialized\n");
630 static int at91rm9200_i2s_prepare(struct snd_pcm_substream *substream)
632 struct snd_soc_pcm_runtime *rtd = substream->private_data;
633 at91rm9200_pcm_dma_params_t *dma_params = rtd->cpu_dai->dma_data;
635 at91_ssc_write(dma_params->ssc->cr, dma_params->mask->ssc_enable);
637 DBG("%s enabled SSC_SR=0x%08lx\n",
638 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "transmit" : "receive",
639 at91_ssc_read(ssc_info[rtd->cpu_dai->id].ssc_base + AT91_SSC_SR));
644 struct snd_soc_cpu_dai at91rm9200_i2s_dai[] = {
645 { .name = "at91rm9200-ssc0/i2s",
647 .type = SND_SOC_DAI_I2S,
648 .suspend = at91rm9200_i2s_suspend,
649 .resume = at91rm9200_i2s_resume,
650 .config_sysclk = at91rm9200_i2s_config_sysclk,
658 .startup = at91rm9200_i2s_startup,
659 .shutdown = at91rm9200_i2s_shutdown,
660 .prepare = at91rm9200_i2s_prepare,
661 .hw_params = at91rm9200_i2s_hw_params,},
663 .mode = &at91rm9200_i2s[0],
664 .num_modes = ARRAY_SIZE(at91rm9200_i2s),},
666 { .name = "at91rm9200-ssc1/i2s",
668 .type = SND_SOC_DAI_I2S,
669 .suspend = at91rm9200_i2s_suspend,
670 .resume = at91rm9200_i2s_resume,
671 .config_sysclk = at91rm9200_i2s_config_sysclk,
679 .startup = at91rm9200_i2s_startup,
680 .shutdown = at91rm9200_i2s_shutdown,
681 .prepare = at91rm9200_i2s_prepare,
682 .hw_params = at91rm9200_i2s_hw_params,},
684 .mode = &at91rm9200_i2s[0],
685 .num_modes = ARRAY_SIZE(at91rm9200_i2s),},
687 { .name = "at91rm9200-ssc2/i2s",
689 .type = SND_SOC_DAI_I2S,
690 .suspend = at91rm9200_i2s_suspend,
691 .resume = at91rm9200_i2s_resume,
692 .config_sysclk = at91rm9200_i2s_config_sysclk,
700 .startup = at91rm9200_i2s_startup,
701 .shutdown = at91rm9200_i2s_shutdown,
702 .prepare = at91rm9200_i2s_prepare,
703 .hw_params = at91rm9200_i2s_hw_params,},
705 .mode = &at91rm9200_i2s[0],
706 .num_modes = ARRAY_SIZE(at91rm9200_i2s),},
710 EXPORT_SYMBOL_GPL(at91rm9200_i2s_dai);
712 /* Module information */
713 MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com");
714 MODULE_DESCRIPTION("AT91RM9200 I2S ASoC Interface");
715 MODULE_LICENSE("GPL");