2 * Driver for Digigram pcxhr compatible soundcards
4 * main file with alsa callbacks
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/slab.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
34 #include <sound/core.h>
35 #include <sound/initval.h>
36 #include <sound/info.h>
37 #include <sound/control.h>
38 #include <sound/pcm.h>
39 #include <sound/pcm_params.h>
41 #include "pcxhr_mixer.h"
42 #include "pcxhr_hwdep.h"
43 #include "pcxhr_core.h"
45 #define DRIVER_NAME "pcxhr"
47 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
48 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
49 MODULE_LICENSE("GPL");
50 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
55 static int mono[SNDRV_CARDS]; /* capture in mono only */
57 module_param_array(index, int, NULL, 0444);
58 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
59 module_param_array(id, charp, NULL, 0444);
60 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
61 module_param_array(enable, bool, NULL, 0444);
62 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
63 module_param_array(mono, bool, NULL, 0444);
64 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
76 static struct pci_device_id pcxhr_ids[] = {
77 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */
78 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */
79 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */
80 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */
81 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */
82 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */
86 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
88 struct board_parameters {
94 static struct board_parameters pcxhr_board_params[] = {
95 [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, },
96 [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, },
97 [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, },
98 [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, },
99 [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, },
100 [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, },
104 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
105 unsigned int* realfreq)
109 if (freq < 6900 || freq > 110250)
111 reg = (28224000 * 10) / freq;
112 reg = (reg + 5) / 10;
114 *pllreg = reg + 0x800;
115 else if (reg < 0x400)
116 *pllreg = reg & 0x1ff;
117 else if (reg < 0x800) {
118 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
121 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
125 *realfreq = ((28224000 * 10) / reg + 5) / 10;
130 #define PCXHR_FREQ_REG_MASK 0x1f
131 #define PCXHR_FREQ_QUARTZ_48000 0x00
132 #define PCXHR_FREQ_QUARTZ_24000 0x01
133 #define PCXHR_FREQ_QUARTZ_12000 0x09
134 #define PCXHR_FREQ_QUARTZ_32000 0x08
135 #define PCXHR_FREQ_QUARTZ_16000 0x04
136 #define PCXHR_FREQ_QUARTZ_8000 0x0c
137 #define PCXHR_FREQ_QUARTZ_44100 0x02
138 #define PCXHR_FREQ_QUARTZ_22050 0x0a
139 #define PCXHR_FREQ_QUARTZ_11025 0x06
140 #define PCXHR_FREQ_PLL 0x05
141 #define PCXHR_FREQ_QUARTZ_192000 0x10
142 #define PCXHR_FREQ_QUARTZ_96000 0x18
143 #define PCXHR_FREQ_QUARTZ_176400 0x14
144 #define PCXHR_FREQ_QUARTZ_88200 0x1c
145 #define PCXHR_FREQ_QUARTZ_128000 0x12
146 #define PCXHR_FREQ_QUARTZ_64000 0x1a
148 #define PCXHR_FREQ_WORD_CLOCK 0x0f
149 #define PCXHR_FREQ_SYNC_AES 0x0e
150 #define PCXHR_FREQ_AES_1 0x07
151 #define PCXHR_FREQ_AES_2 0x0b
152 #define PCXHR_FREQ_AES_3 0x03
153 #define PCXHR_FREQ_AES_4 0x0d
155 #define PCXHR_MODIFY_CLOCK_S_BIT 0x04
157 #define PCXHR_IRQ_TIMER_FREQ 92000
158 #define PCXHR_IRQ_TIMER_PERIOD 48
160 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
161 unsigned int *reg, unsigned int *freq)
163 unsigned int val, realfreq, pllreg;
164 struct pcxhr_rmh rmh;
168 switch (mgr->use_clock_type) {
169 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
171 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
172 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
173 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
174 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
175 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
176 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
177 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
178 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
179 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
180 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
181 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
182 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
183 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
184 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
185 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
187 val = PCXHR_FREQ_PLL;
188 /* get the value for the pll register */
189 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
192 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
193 rmh.cmd[0] |= IO_NUM_REG_GENCLK;
194 rmh.cmd[1] = pllreg & MASK_DSP_WORD;
195 rmh.cmd[2] = pllreg >> 24;
197 err = pcxhr_send_msg(mgr, &rmh);
200 "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
206 case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break;
207 case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break;
208 case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break;
209 case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break;
210 case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break;
211 case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break;
212 default : return -EINVAL;
220 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
222 unsigned int val, realfreq, speed;
223 struct pcxhr_rmh rmh;
227 return 0; /* nothing to do */
229 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
233 /* codec speed modes */
235 speed = 0; /* single speed */
236 else if (rate < 100000)
237 speed = 1; /* dual speed */
239 speed = 2; /* quad speed */
240 if (mgr->codec_speed != speed) {
241 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
242 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
243 err = pcxhr_send_msg(mgr, &rmh);
247 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
248 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
251 err = pcxhr_send_msg(mgr, &rmh);
255 /* set the new frequency */
256 snd_printdd("clock register : set %x\n", val);
257 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
260 mgr->sample_rate_real = realfreq;
261 mgr->cur_clock_type = mgr->use_clock_type;
263 /* unmute after codec speed modes */
264 if (mgr->codec_speed != speed) {
265 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
266 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
267 err = pcxhr_send_msg(mgr, &rmh);
270 mgr->codec_speed = speed; /* save new codec speed */
274 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
275 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
276 if (rate < PCXHR_IRQ_TIMER_FREQ)
277 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
279 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
282 err = pcxhr_send_msg(mgr, &rmh);
286 snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
291 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
294 struct pcxhr_rmh rmh;
298 switch (clock_type) {
299 case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break;
300 case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break;
301 case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break;
302 case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break;
303 case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break;
304 case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break;
305 default : return -EINVAL;
307 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
309 rmh.cmd[0] |= IO_NUM_REG_STATUS;
310 if (mgr->last_reg_stat != reg) {
312 err = pcxhr_send_msg(mgr, &rmh);
315 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
316 mgr->last_reg_stat = reg;
318 rmh.cmd[1] = REG_STATUS_CURRENT;
319 err = pcxhr_send_msg(mgr, &rmh);
322 switch (rmh.stat[1] & 0x0f) {
323 case REG_STATUS_SYNC_32000 : rate = 32000; break;
324 case REG_STATUS_SYNC_44100 : rate = 44100; break;
325 case REG_STATUS_SYNC_48000 : rate = 48000; break;
326 case REG_STATUS_SYNC_64000 : rate = 64000; break;
327 case REG_STATUS_SYNC_88200 : rate = 88200; break;
328 case REG_STATUS_SYNC_96000 : rate = 96000; break;
329 case REG_STATUS_SYNC_128000 : rate = 128000; break;
330 case REG_STATUS_SYNC_176400 : rate = 176400; break;
331 case REG_STATUS_SYNC_192000 : rate = 192000; break;
334 snd_printdd("External clock is at %d Hz\n", rate);
341 * start or stop playback/capture substream
343 static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
346 struct snd_pcxhr *chip;
347 struct pcxhr_rmh rmh;
348 int stream_mask, start;
350 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
353 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
354 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
359 if (!stream->substream)
362 stream->timer_abs_periods = 0;
363 stream->timer_period_frag = 0; /* reset theoretical stream pos */
364 stream->timer_buf_periods = 0;
365 stream->timer_is_synced = 0;
367 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
369 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
370 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
371 stream->pipe->first_audio, 0, stream_mask);
373 chip = snd_pcm_substream_chip(stream->substream);
375 err = pcxhr_send_msg(chip->mgr, &rmh);
377 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
378 stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
382 #define HEADER_FMT_BASE_LIN 0xfed00000
383 #define HEADER_FMT_BASE_FLOAT 0xfad00000
384 #define HEADER_FMT_INTEL 0x00008000
385 #define HEADER_FMT_24BITS 0x00004000
386 #define HEADER_FMT_16BITS 0x00002000
387 #define HEADER_FMT_UPTO11 0x00000200
388 #define HEADER_FMT_UPTO32 0x00000100
389 #define HEADER_FMT_MONO 0x00000080
391 static int pcxhr_set_format(struct pcxhr_stream *stream)
393 int err, is_capture, sample_rate, stream_num;
394 struct snd_pcxhr *chip;
395 struct pcxhr_rmh rmh;
398 switch (stream->format) {
399 case SNDRV_PCM_FORMAT_U8:
400 header = HEADER_FMT_BASE_LIN;
402 case SNDRV_PCM_FORMAT_S16_LE:
403 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
405 case SNDRV_PCM_FORMAT_S16_BE:
406 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
408 case SNDRV_PCM_FORMAT_S24_3LE:
409 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
411 case SNDRV_PCM_FORMAT_S24_3BE:
412 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
414 case SNDRV_PCM_FORMAT_FLOAT_LE:
415 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
418 snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
421 chip = snd_pcm_substream_chip(stream->substream);
423 sample_rate = chip->mgr->sample_rate;
424 if (sample_rate <= 32000 && sample_rate !=0) {
425 if (sample_rate <= 11025)
426 header |= HEADER_FMT_UPTO11;
428 header |= HEADER_FMT_UPTO32;
430 if (stream->channels == 1)
431 header |= HEADER_FMT_MONO;
433 is_capture = stream->pipe->is_capture;
434 stream_num = is_capture ? 0 : stream->substream->number;
436 pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
437 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
441 rmh.cmd[2] = header >> 8;
442 rmh.cmd[3] = (header & 0xff) << 16;
444 err = pcxhr_send_msg(chip->mgr, &rmh);
446 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
450 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
452 int err, is_capture, stream_num;
453 struct pcxhr_rmh rmh;
454 struct snd_pcm_substream *subs = stream->substream;
455 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
457 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
458 stream_num = is_capture ? 0 : subs->number;
460 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
461 is_capture ? 'c' : 'p',
462 chip->chip_idx, (void*)subs->runtime->dma_addr,
463 subs->runtime->dma_bytes, subs->number);
465 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
466 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
468 snd_assert(subs->runtime->dma_bytes < 0x200000); /* max buffer size is 2 MByte */
469 rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */
470 rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */
471 rmh.cmd[2] |= 1<<19; /* this is a circular buffer */
472 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */
474 err = pcxhr_send_msg(chip->mgr, &rmh);
476 snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
482 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
484 struct pcxhr_rmh rmh;
486 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
487 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
488 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
489 1<<stream->pipe->first_audio);
490 err = pcxhr_send_msg(chip->mgr, &rmh);
492 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
493 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
495 snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
500 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
501 struct pcxhr_pipe **pipe)
503 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
504 *pipe = stream->pipe;
510 static void pcxhr_trigger_tasklet(unsigned long arg)
514 struct pcxhr_pipe *pipe;
515 struct snd_pcxhr *chip;
516 struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
517 int capture_mask = 0;
518 int playback_mask = 0;
520 #ifdef CONFIG_SND_DEBUG_DETECT
521 struct timeval my_tv1, my_tv2;
522 do_gettimeofday(&my_tv1);
524 mutex_lock(&mgr->setup_mutex);
526 /* check the pipes concerned and build pipe_array */
527 for (i = 0; i < mgr->num_cards; i++) {
529 for (j = 0; j < chip->nb_streams_capt; j++) {
530 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
531 capture_mask |= (1 << pipe->first_audio);
533 for (j = 0; j < chip->nb_streams_play; j++) {
534 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
535 playback_mask |= (1 << pipe->first_audio);
536 break; /* add only once, as all playback streams of
537 * one chip use the same pipe
542 if (capture_mask == 0 && playback_mask == 0) {
543 mutex_unlock(&mgr->setup_mutex);
544 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
548 snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
549 playback_mask, capture_mask);
551 /* synchronous stop of all the pipes concerned */
552 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
554 mutex_unlock(&mgr->setup_mutex);
555 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
556 playback_mask, capture_mask);
560 /* unfortunately the dsp lost format and buffer info with the stop pipe */
561 for (i = 0; i < mgr->num_cards; i++) {
562 struct pcxhr_stream *stream;
564 for (j = 0; j < chip->nb_streams_capt; j++) {
565 stream = &chip->capture_stream[j];
566 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
567 err = pcxhr_set_format(stream);
568 err = pcxhr_update_r_buffer(stream);
571 for (j = 0; j < chip->nb_streams_play; j++) {
572 stream = &chip->playback_stream[j];
573 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
574 err = pcxhr_set_format(stream);
575 err = pcxhr_update_r_buffer(stream);
579 /* start all the streams */
580 for (i = 0; i < mgr->num_cards; i++) {
581 struct pcxhr_stream *stream;
583 for (j = 0; j < chip->nb_streams_capt; j++) {
584 stream = &chip->capture_stream[j];
585 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
586 err = pcxhr_set_stream_state(stream);
588 for (j = 0; j < chip->nb_streams_play; j++) {
589 stream = &chip->playback_stream[j];
590 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
591 err = pcxhr_set_stream_state(stream);
595 /* synchronous start of all the pipes concerned */
596 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
598 mutex_unlock(&mgr->setup_mutex);
599 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
600 playback_mask, capture_mask);
604 /* put the streams into the running state now (increment pointer by interrupt) */
605 spin_lock_irqsave(&mgr->lock, flags);
606 for ( i =0; i < mgr->num_cards; i++) {
607 struct pcxhr_stream *stream;
609 for(j = 0; j < chip->nb_streams_capt; j++) {
610 stream = &chip->capture_stream[j];
611 if(stream->status == PCXHR_STREAM_STATUS_STARTED)
612 stream->status = PCXHR_STREAM_STATUS_RUNNING;
614 for (j = 0; j < chip->nb_streams_play; j++) {
615 stream = &chip->playback_stream[j];
616 if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
617 /* playback will already have advanced ! */
618 stream->timer_period_frag += PCXHR_GRANULARITY;
619 stream->status = PCXHR_STREAM_STATUS_RUNNING;
623 spin_unlock_irqrestore(&mgr->lock, flags);
625 mutex_unlock(&mgr->setup_mutex);
627 #ifdef CONFIG_SND_DEBUG_DETECT
628 do_gettimeofday(&my_tv2);
629 snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
630 my_tv2.tv_usec - my_tv1.tv_usec, err);
638 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
640 struct pcxhr_stream *stream;
641 struct snd_pcm_substream *s;
645 case SNDRV_PCM_TRIGGER_START:
646 snd_printdd("SNDRV_PCM_TRIGGER_START\n");
648 snd_pcm_group_for_each_entry(s, subs) {
649 stream = s->runtime->private_data;
650 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
651 snd_pcm_trigger_done(s, subs);
655 snd_printdd("Only one Substream %c %d\n",
656 stream->pipe->is_capture ? 'C' : 'P',
657 stream->pipe->first_audio);
658 if (pcxhr_set_format(stream))
660 if (pcxhr_update_r_buffer(stream))
663 if (pcxhr_set_stream_state(stream))
665 stream->status = PCXHR_STREAM_STATUS_RUNNING;
667 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
668 tasklet_hi_schedule(&chip->mgr->trigger_taskq);
671 case SNDRV_PCM_TRIGGER_STOP:
672 snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
673 snd_pcm_group_for_each_entry(s, subs) {
674 stream = s->runtime->private_data;
675 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
676 if (pcxhr_set_stream_state(stream))
678 snd_pcm_trigger_done(s, subs);
681 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
682 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
691 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
693 struct pcxhr_rmh rmh;
696 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
698 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */
699 rmh.cmd[0] |= PCXHR_GRANULARITY;
701 err = pcxhr_send_msg(mgr, &rmh);
703 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
708 * prepare callback for all pcms
710 static int pcxhr_prepare(struct snd_pcm_substream *subs)
712 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
713 struct pcxhr_mgr *mgr = chip->mgr;
715 struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
719 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
720 subs->runtime->period_size, subs->runtime->periods,
721 subs->runtime->buffer_size);
724 if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
725 snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
726 (unsigned int)subs->runtime->period_size);
731 mutex_lock(&mgr->setup_mutex);
734 /* if the stream was stopped before, format and buffer were reset */
736 if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
737 err = pcxhr_set_format(stream);
739 err = pcxhr_update_r_buffer(stream);
744 /* only the first stream can choose the sample rate */
745 /* the further opened streams will be limited to its frequency (see open) */
746 /* set the clock only once (first stream) */
747 if (mgr->sample_rate != subs->runtime->rate) {
748 err = pcxhr_set_clock(mgr, subs->runtime->rate);
751 if (mgr->sample_rate == 0)
752 /* start the DSP-timer */
753 err = pcxhr_hardware_timer(mgr, 1);
754 mgr->sample_rate = subs->runtime->rate;
756 } while(0); /* do only once (so we can use break instead of goto) */
758 mutex_unlock(&mgr->setup_mutex);
765 * HW_PARAMS callback for all pcms
767 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
768 struct snd_pcm_hw_params *hw)
770 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
771 struct pcxhr_mgr *mgr = chip->mgr;
772 struct pcxhr_stream *stream = subs->runtime->private_data;
773 snd_pcm_format_t format;
777 /* set up channels */
778 channels = params_channels(hw);
780 /* set up format for the stream */
781 format = params_format(hw);
783 mutex_lock(&mgr->setup_mutex);
785 stream->channels = channels;
786 stream->format = format;
788 /* set the format to the board */
790 err = pcxhr_set_format(stream);
792 mutex_unlock(&mgr->setup_mutex);
796 /* allocate buffer */
797 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
801 err = pcxhr_update_r_buffer(stream);
804 mutex_unlock(&mgr->setup_mutex);
809 static int pcxhr_hw_free(struct snd_pcm_substream *subs)
811 snd_pcm_lib_free_pages(subs);
817 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
819 static struct snd_pcm_hardware pcxhr_caps =
821 .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
822 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
823 0 /*SNDRV_PCM_INFO_PAUSE*/),
824 .formats = ( SNDRV_PCM_FMTBIT_U8 |
825 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
826 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
827 SNDRV_PCM_FMTBIT_FLOAT_LE ),
828 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
833 .buffer_bytes_max = (32*1024),
834 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
835 .period_bytes_min = (2*PCXHR_GRANULARITY),
836 .period_bytes_max = (16*1024),
838 .periods_max = (32*1024/PCXHR_GRANULARITY),
842 static int pcxhr_open(struct snd_pcm_substream *subs)
844 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
845 struct pcxhr_mgr *mgr = chip->mgr;
846 struct snd_pcm_runtime *runtime = subs->runtime;
847 struct pcxhr_stream *stream;
850 mutex_lock(&mgr->setup_mutex);
852 /* copy the struct snd_pcm_hardware struct */
853 runtime->hw = pcxhr_caps;
855 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
856 snd_printdd("pcxhr_open playback chip%d subs%d\n",
857 chip->chip_idx, subs->number);
859 stream = &chip->playback_stream[subs->number];
861 snd_printdd("pcxhr_open capture chip%d subs%d\n",
862 chip->chip_idx, subs->number);
864 if (mgr->mono_capture)
865 runtime->hw.channels_max = 1;
867 runtime->hw.channels_min = 2;
868 stream = &chip->capture_stream[subs->number];
870 if (stream->status != PCXHR_STREAM_STATUS_FREE){
872 snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
873 chip->chip_idx, subs->number);
874 mutex_unlock(&mgr->setup_mutex);
878 /* if a sample rate is already used or fixed by external clock,
879 * the stream cannot change
881 if (mgr->sample_rate)
882 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
884 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
886 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
888 external_rate == 0) {
889 /* cannot detect the external clock rate */
890 mutex_unlock(&mgr->setup_mutex);
893 runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
897 stream->status = PCXHR_STREAM_STATUS_OPEN;
898 stream->substream = subs;
899 stream->channels = 0; /* not configured yet */
901 runtime->private_data = stream;
903 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
904 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
906 mgr->ref_count_rate++;
908 mutex_unlock(&mgr->setup_mutex);
913 static int pcxhr_close(struct snd_pcm_substream *subs)
915 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
916 struct pcxhr_mgr *mgr = chip->mgr;
917 struct pcxhr_stream *stream = subs->runtime->private_data;
919 mutex_lock(&mgr->setup_mutex);
921 snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
923 /* sample rate released */
924 if (--mgr->ref_count_rate == 0) {
925 mgr->sample_rate = 0; /* the sample rate is no more locked */
926 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
929 stream->status = PCXHR_STREAM_STATUS_FREE;
930 stream->substream = NULL;
932 mutex_unlock(&mgr->setup_mutex);
938 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
941 u_int32_t timer_period_frag;
942 int timer_buf_periods;
943 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
944 struct snd_pcm_runtime *runtime = subs->runtime;
945 struct pcxhr_stream *stream = runtime->private_data;
947 spin_lock_irqsave(&chip->mgr->lock, flags);
949 /* get the period fragment and the nb of periods in the buffer */
950 timer_period_frag = stream->timer_period_frag;
951 timer_buf_periods = stream->timer_buf_periods;
953 spin_unlock_irqrestore(&chip->mgr->lock, flags);
955 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
960 static struct snd_pcm_ops pcxhr_ops = {
962 .close = pcxhr_close,
963 .ioctl = snd_pcm_lib_ioctl,
964 .prepare = pcxhr_prepare,
965 .hw_params = pcxhr_hw_params,
966 .hw_free = pcxhr_hw_free,
967 .trigger = pcxhr_trigger,
968 .pointer = pcxhr_stream_pointer,
973 int pcxhr_create_pcm(struct snd_pcxhr *chip)
979 sprintf(name, "pcxhr %d", chip->chip_idx);
980 if ((err = snd_pcm_new(chip->card, name, 0,
981 chip->nb_streams_play,
982 chip->nb_streams_capt, &pcm)) < 0) {
983 snd_printk(KERN_ERR "cannot create pcm %s\n", name);
986 pcm->private_data = chip;
988 if (chip->nb_streams_play)
989 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
990 if (chip->nb_streams_capt)
991 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
994 strcpy(pcm->name, name);
996 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
997 snd_dma_pci_data(chip->mgr->pci),
1003 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1009 static int pcxhr_chip_dev_free(struct snd_device *device)
1011 struct snd_pcxhr *chip = device->device_data;
1012 return pcxhr_chip_free(chip);
1018 static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
1021 struct snd_pcxhr *chip;
1022 static struct snd_device_ops ops = {
1023 .dev_free = pcxhr_chip_dev_free,
1026 mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1028 snd_printk(KERN_ERR "cannot allocate chip\n");
1033 chip->chip_idx = idx;
1036 if (idx < mgr->playback_chips)
1037 /* stereo or mono streams */
1038 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1040 if (idx < mgr->capture_chips) {
1041 if (mgr->mono_capture)
1042 chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */
1044 chip->nb_streams_capt = 1; /* or 1 stereo stream */
1047 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1048 pcxhr_chip_free(chip);
1052 snd_card_set_dev(card, &mgr->pci->dev);
1057 /* proc interface */
1058 static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1060 struct snd_pcxhr *chip = entry->private_data;
1061 struct pcxhr_mgr *mgr = chip->mgr;
1063 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1065 /* stats available when embedded DSP is running */
1066 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1067 struct pcxhr_rmh rmh;
1068 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1069 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1070 short ver_build = mgr->dsp_version & 0xff;
1071 snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
1072 snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
1073 if (mgr->board_has_analog)
1074 snd_iprintf(buffer, "analog io available\n");
1076 snd_iprintf(buffer, "digital only board\n");
1078 /* calc cpu load of the dsp */
1079 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1080 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1081 int cur = rmh.stat[0];
1082 int ref = rmh.stat[1];
1084 if (mgr->sample_rate_real != 0 &&
1085 mgr->sample_rate_real != 48000) {
1086 ref = (ref * 48000) / mgr->sample_rate_real;
1087 if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
1090 cur = 100 - (100 * cur) / ref;
1091 snd_iprintf(buffer, "cpu load %d%%\n", cur);
1092 snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
1093 rmh.stat[2], rmh.stat[3]);
1096 snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
1097 snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
1098 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1099 mgr->async_err_pipe_xrun);
1100 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1101 mgr->async_err_stream_xrun);
1102 snd_iprintf(buffer, "dsp async last other error : %x\n",
1103 mgr->async_err_other_last);
1104 /* debug zone dsp */
1105 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1107 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1109 rmh.cmd_idx = CMD_LAST_INDEX;
1110 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1112 for (i = 0; i < rmh.stat_len; i++)
1113 snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]);
1116 snd_iprintf(buffer, "no firmware loaded\n");
1117 snd_iprintf(buffer, "\n");
1119 static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1121 struct snd_pcxhr *chip = entry->private_data;
1122 struct pcxhr_mgr *mgr = chip->mgr;
1123 static char *texts[7] = {
1124 "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
1127 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1128 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
1129 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
1131 /* commands available when embedded DSP is running */
1132 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1133 int i, err, sample_rate;
1134 for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
1135 err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1138 snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
1141 snd_iprintf(buffer, "no firmware loaded\n");
1142 snd_iprintf(buffer, "\n");
1145 static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
1147 struct snd_info_entry *entry;
1149 if (! snd_card_proc_new(chip->card, "info", &entry))
1150 snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
1151 if (! snd_card_proc_new(chip->card, "sync", &entry))
1152 snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
1154 /* end of proc interface */
1157 * release all the cards assigned to a manager instance
1159 static int pcxhr_free(struct pcxhr_mgr *mgr)
1163 for (i = 0; i < mgr->num_cards; i++) {
1165 snd_card_free(mgr->chip[i]->card);
1168 /* reset board if some firmware was loaded */
1169 if(mgr->dsp_loaded) {
1170 pcxhr_reset_board(mgr);
1171 snd_printdd("reset pcxhr !\n");
1176 free_irq(mgr->irq, mgr);
1178 pci_release_regions(mgr->pci);
1180 /* free hostport purgebuffer */
1181 if (mgr->hostport.area) {
1182 snd_dma_free_pages(&mgr->hostport);
1183 mgr->hostport.area = NULL;
1188 pci_disable_device(mgr->pci);
1194 * probe function - creates the card manager
1196 static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1199 struct pcxhr_mgr *mgr;
1205 if (dev >= SNDRV_CARDS)
1207 if (! enable[dev]) {
1212 /* enable PCI device */
1213 if ((err = pci_enable_device(pci)) < 0)
1215 pci_set_master(pci);
1217 /* check if we can restrict PCI DMA transfers to 32 bits */
1218 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) {
1219 snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
1220 pci_disable_device(pci);
1224 /* alloc card manager */
1225 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1227 pci_disable_device(pci);
1231 snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV);
1232 card_name = pcxhr_board_params[pci_id->driver_data].board_name;
1233 mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
1234 mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips;
1235 mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num;
1236 mgr->mono_capture = mono[dev];
1238 /* resource assignment */
1239 if ((err = pci_request_regions(pci, card_name)) < 0) {
1241 pci_disable_device(pci);
1244 for (i = 0; i < 3; i++)
1245 mgr->port[i] = pci_resource_start(pci, i);
1250 if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED,
1252 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1256 mgr->irq = pci->irq;
1258 sprintf(mgr->shortname, "Digigram %s", card_name);
1259 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
1260 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1263 spin_lock_init(&mgr->lock);
1264 spin_lock_init(&mgr->msg_lock);
1266 /* init setup mutex*/
1267 mutex_init(&mgr->setup_mutex);
1270 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
1271 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
1272 mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1273 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
1280 for (i=0; i < PCXHR_MAX_CARDS; i++) {
1281 struct snd_card *card;
1285 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1292 idx = index[dev] + i;
1294 snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
1295 card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
1298 snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
1303 strcpy(card->driver, DRIVER_NAME);
1304 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1305 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1307 if ((err = pcxhr_create(mgr, card, i)) < 0) {
1313 /* init proc interface only for chip0 */
1314 pcxhr_proc_init(mgr->chip[i]);
1316 if ((err = snd_card_register(card)) < 0) {
1322 /* create hostport purgebuffer */
1323 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1324 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1325 size, &mgr->hostport) < 0) {
1329 /* init purgebuffer */
1330 memset(mgr->hostport.area, 0, size);
1332 /* create a DSP loader */
1333 err = pcxhr_setup_firmware(mgr);
1339 pci_set_drvdata(pci, mgr);
1344 static void __devexit pcxhr_remove(struct pci_dev *pci)
1346 pcxhr_free(pci_get_drvdata(pci));
1347 pci_set_drvdata(pci, NULL);
1350 static struct pci_driver driver = {
1351 .name = "Digigram pcxhr",
1352 .id_table = pcxhr_ids,
1353 .probe = pcxhr_probe,
1354 .remove = __devexit_p(pcxhr_remove),
1357 static int __init pcxhr_module_init(void)
1359 return pci_register_driver(&driver);
1362 static void __exit pcxhr_module_exit(void)
1364 pci_unregister_driver(&driver);
1367 module_init(pcxhr_module_init)
1368 module_exit(pcxhr_module_exit)