err.no Git - linux-2.6/blob - sound/pci/intel8x0m.c

   1 /*
   2  *   ALSA modem driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *   This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version
   7  *   of ALSA ICH sound driver intel8x0.c .
   8  *
   9  *
  10  *   This program is free software; you can redistribute it and/or modify
  11  *   it under the terms of the GNU General Public License as published by
  12  *   the Free Software Foundation; either version 2 of the License, or
  13  *   (at your option) any later version.
  14  *
  15  *   This program is distributed in the hope that it will be useful,
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *   GNU General Public License for more details.
  19  *
  20  *   You should have received a copy of the GNU General Public License
  21  *   along with this program; if not, write to the Free Software
  22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  */
  25
  26 #include <sound/driver.h>
  27 #include <asm/io.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/slab.h>
  33 #include <linux/moduleparam.h>
  34 #include <sound/core.h>
  35 #include <sound/pcm.h>
  36 #include <sound/ac97_codec.h>
  37 #include <sound/info.h>
  38 #include <sound/control.h>
  39 #include <sound/initval.h>
  40
  41 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  42 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems");
  43 MODULE_LICENSE("GPL");
  44 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  45                 "{Intel,82901AB-ICH0},"
  46                 "{Intel,82801BA-ICH2},"
  47                 "{Intel,82801CA-ICH3},"
  48                 "{Intel,82801DB-ICH4},"
  49                 "{Intel,ICH5},"
  50                 "{Intel,ICH6},"
  51                 "{Intel,ICH7},"
  52                 "{Intel,MX440},"
  53                 "{SiS,7013},"
  54                 "{NVidia,NForce Modem},"
  55                 "{NVidia,NForce2 Modem},"
  56                 "{NVidia,NForce2s Modem},"
  57                 "{NVidia,NForce3 Modem},"
  58                 "{AMD,AMD768}}");
  59
  60 static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  63 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard.");
  71 module_param_array(ac97_clock, int, NULL, 0444);
  72 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  73
  74 /*
  75  *  Direct registers
  76  */
  77
  78 #ifndef PCI_DEVICE_ID_INTEL_82801_6
  79 #define PCI_DEVICE_ID_INTEL_82801_6     0x2416
  80 #endif
  81 #ifndef PCI_DEVICE_ID_INTEL_82901_6
  82 #define PCI_DEVICE_ID_INTEL_82901_6     0x2426
  83 #endif
  84 #ifndef PCI_DEVICE_ID_INTEL_82801BA_6
  85 #define PCI_DEVICE_ID_INTEL_82801BA_6   0x2446
  86 #endif
  87 #ifndef PCI_DEVICE_ID_INTEL_440MX_6
  88 #define PCI_DEVICE_ID_INTEL_440MX_6     0x7196
  89 #endif
  90 #ifndef PCI_DEVICE_ID_INTEL_ICH3_6
  91 #define PCI_DEVICE_ID_INTEL_ICH3_6      0x2486
  92 #endif
  93 #ifndef PCI_DEVICE_ID_INTEL_ICH4_6
  94 #define PCI_DEVICE_ID_INTEL_ICH4_6      0x24c6
  95 #endif
  96 #ifndef PCI_DEVICE_ID_INTEL_ICH5_6
  97 #define PCI_DEVICE_ID_INTEL_ICH5_6      0x24d6
  98 #endif
  99 #ifndef PCI_DEVICE_ID_INTEL_ICH6_6
 100 #define PCI_DEVICE_ID_INTEL_ICH6_6      0x266d
 101 #endif
 102 #ifndef PCI_DEVICE_ID_INTEL_ICH7_6
 103 #define PCI_DEVICE_ID_INTEL_ICH7_6      0x27dd
 104 #endif
 105 #ifndef PCI_DEVICE_ID_SI_7013
 106 #define PCI_DEVICE_ID_SI_7013           0x7013
 107 #endif
 108 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_MODEM
 109 #define PCI_DEVICE_ID_NVIDIA_MCP_MODEM  0x01c1
 110 #endif
 111 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_MODEM
 112 #define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069
 113 #endif
 114 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM
 115 #define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089
 116 #endif
 117 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_MODEM
 118 #define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9
 119 #endif
 120
 121
 122 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
 123
 124 #define ICHREG(x) ICH_REG_##x
 125
 126 #define DEFINE_REGSET(name,base) \
 127 enum { \
 128         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 129         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 130         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 131         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 132         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 133         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 134         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 135 };
 136
 137 /* busmaster blocks */
 138 DEFINE_REGSET(OFF, 0);          /* offset */
 139
 140 /* values for each busmaster block */
 141
 142 /* LVI */
 143 #define ICH_REG_LVI_MASK                0x1f
 144
 145 /* SR */
 146 #define ICH_FIFOE                       0x10    /* FIFO error */
 147 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 148 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 149 #define ICH_CELV                        0x02    /* current equals last valid */
 150 #define ICH_DCH                         0x01    /* DMA controller halted */
 151
 152 /* PIV */
 153 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 154
 155 /* CR */
 156 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 157 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 158 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 159 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 160 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 161
 162
 163 /* global block */
 164 #define ICH_REG_GLOB_CNT                0x3c    /* dword - global control */
 165 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 166 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 167 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 168 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 169 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 170 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 171 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 172 #define ICH_REG_GLOB_STA                0x40    /* dword - global status */
 173 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 174 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 175 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 176 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 177 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 178 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 179 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 180 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 181 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 182 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 183 #define   ICH_RCS               0x00008000      /* read completion status */
 184 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 185 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 186 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 187 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 188 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 189 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 190 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 191 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 192 #define   ICH_POINT             0x00000040      /* playback interrupt */
 193 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 194 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 195 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 196 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 197 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 198 #define ICH_REG_ACC_SEMA                0x44    /* byte - codec write semaphore */
 199 #define   ICH_CAS               0x01            /* codec access semaphore */
 200
 201 #define ICH_MAX_FRAGS           32              /* max hw frags */
 202
 203
 204 /*
 205  *
 206  */
 207
 208 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
 209 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
 210
 211 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 212
 213 typedef struct {
 214         unsigned int ichd;                      /* ich device number */
 215         unsigned long reg_offset;               /* offset to bmaddr */
 216         u32 *bdbar;                             /* CPU address (32bit) */
 217         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 218         snd_pcm_substream_t *substream;
 219         unsigned int physbuf;                   /* physical address (32bit) */
 220         unsigned int size;
 221         unsigned int fragsize;
 222         unsigned int fragsize1;
 223         unsigned int position;
 224         int frags;
 225         int lvi;
 226         int lvi_frag;
 227         int civ;
 228         int ack;
 229         int ack_reload;
 230         unsigned int ack_bit;
 231         unsigned int roff_sr;
 232         unsigned int roff_picb;
 233         unsigned int int_sta_mask;              /* interrupt status mask */
 234         unsigned int ali_slot;                  /* ALI DMA slot */
 235         ac97_t *ac97;
 236 } ichdev_t;
 237
 238 typedef struct _snd_intel8x0m intel8x0_t;
 239
 240 struct _snd_intel8x0m {
 241         unsigned int device_type;
 242
 243         int irq;
 244
 245         unsigned int mmio;
 246         unsigned long addr;
 247         void __iomem *remap_addr;
 248         unsigned int bm_mmio;
 249         unsigned long bmaddr;
 250         void __iomem *remap_bmaddr;
 251
 252         struct pci_dev *pci;
 253         snd_card_t *card;
 254
 255         int pcm_devs;
 256         snd_pcm_t *pcm[2];
 257         ichdev_t ichd[2];
 258
 259         unsigned int in_ac97_init: 1;
 260
 261         ac97_bus_t *ac97_bus;
 262         ac97_t *ac97;
 263
 264         spinlock_t reg_lock;
 265
 266         struct snd_dma_buffer bdbars;
 267         u32 bdbars_count;
 268         u32 int_sta_reg;                /* interrupt status register */
 269         u32 int_sta_mask;               /* interrupt status mask */
 270         unsigned int pcm_pos_shift;
 271 };
 272
 273 static struct pci_device_id snd_intel8x0m_ids[] = {
 274         { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 275         { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 276         { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 277         { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 278         { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
 279         { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
 280         { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */
 281         { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */
 282         { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 283         { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 284         { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7013 */
 285         { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
 286         { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
 287         { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
 288         { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
 289 #if 0
 290         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 291         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 292 #endif
 293         { 0, }
 294 };
 295 static int snd_intel8x0m_switch_default_get(snd_kcontrol_t *kcontrol,
 296                                             snd_ctl_elem_value_t *ucontrol);
 297 static int snd_intel8x0m_switch_default_put(snd_kcontrol_t *kcontrol,
 298                                             snd_ctl_elem_value_t *ucontrol);
 299 static int snd_intel8x0m_switch_default_info(snd_kcontrol_t *kcontrol,
 300                                              snd_ctl_elem_info_t *uinfo);
 301
 302 #define PRIVATE_VALUE_INITIALIZER(r,m) (((r) & 0xffff) << 16 | ((m) & 0xffff))
 303 #define PRIVATE_VALUE_MASK(control) ((control)->private_value & 0xffff)
 304 #define PRIVATE_VALUE_REG(control) (((control)->private_value >> 16) & 0xffff)
 305
 306 static snd_kcontrol_new_t snd_intel8x0m_mixer_switches[] __devinitdata = {
 307   { .name  = "Off-hook Switch",
 308     .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 309     .info  = snd_intel8x0m_switch_default_info,
 310     .get   = snd_intel8x0m_switch_default_get,
 311     .put   = snd_intel8x0m_switch_default_put,
 312     .private_value = PRIVATE_VALUE_INITIALIZER(AC97_GPIO_STATUS,AC97_GPIO_LINE1_OH)
 313   }
 314 };
 315
 316 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
 317
 318 static int snd_intel8x0m_switch_default_info(snd_kcontrol_t *kcontrol,
 319                                              snd_ctl_elem_info_t *uinfo)
 320 {
 321         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 322         uinfo->count = 1;
 323         uinfo->value.integer.min = 0;
 324         uinfo->value.integer.max = 1;
 325         return 0;
 326 }
 327
 328 static int snd_intel8x0m_switch_default_get(snd_kcontrol_t *kcontrol,
 329                                             snd_ctl_elem_value_t *ucontrol)
 330 {
 331         unsigned short mask = PRIVATE_VALUE_MASK(kcontrol);
 332         unsigned short reg = PRIVATE_VALUE_REG(kcontrol);
 333         intel8x0_t *chip = snd_kcontrol_chip(kcontrol);
 334         unsigned int status;
 335         status = snd_ac97_read(chip->ac97, reg) & mask ? 1 : 0;
 336         ucontrol->value.integer.value[0] = status;
 337         return 0;
 338 }
 339 static int snd_intel8x0m_switch_default_put(snd_kcontrol_t *kcontrol,
 340                                             snd_ctl_elem_value_t *ucontrol)
 341 {
 342         unsigned short mask = PRIVATE_VALUE_MASK(kcontrol);
 343         unsigned short reg = PRIVATE_VALUE_REG(kcontrol);
 344         intel8x0_t *chip = snd_kcontrol_chip(kcontrol);
 345         unsigned short new_status = ucontrol->value.integer.value[0] ? mask : ~mask;
 346         return snd_ac97_update_bits(chip->ac97, reg,
 347                                     mask, new_status);
 348 }
 349 /*
 350  *  Lowlevel I/O - busmaster
 351  */
 352
 353 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 354 {
 355         if (chip->bm_mmio)
 356                 return readb(chip->remap_bmaddr + offset);
 357         else
 358                 return inb(chip->bmaddr + offset);
 359 }
 360
 361 static u16 igetword(intel8x0_t *chip, u32 offset)
 362 {
 363         if (chip->bm_mmio)
 364                 return readw(chip->remap_bmaddr + offset);
 365         else
 366                 return inw(chip->bmaddr + offset);
 367 }
 368
 369 static u32 igetdword(intel8x0_t *chip, u32 offset)
 370 {
 371         if (chip->bm_mmio)
 372                 return readl(chip->remap_bmaddr + offset);
 373         else
 374                 return inl(chip->bmaddr + offset);
 375 }
 376
 377 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 378 {
 379         if (chip->bm_mmio)
 380                 writeb(val, chip->remap_bmaddr + offset);
 381         else
 382                 outb(val, chip->bmaddr + offset);
 383 }
 384
 385 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 386 {
 387         if (chip->bm_mmio)
 388                 writew(val, chip->remap_bmaddr + offset);
 389         else
 390                 outw(val, chip->bmaddr + offset);
 391 }
 392
 393 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 394 {
 395         if (chip->bm_mmio)
 396                 writel(val, chip->remap_bmaddr + offset);
 397         else
 398                 outl(val, chip->bmaddr + offset);
 399 }
 400
 401 /*
 402  *  Lowlevel I/O - AC'97 registers
 403  */
 404
 405 static u16 iagetword(intel8x0_t *chip, u32 offset)
 406 {
 407         if (chip->mmio)
 408                 return readw(chip->remap_addr + offset);
 409         else
 410                 return inw(chip->addr + offset);
 411 }
 412
 413 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 414 {
 415         if (chip->mmio)
 416                 writew(val, chip->remap_addr + offset);
 417         else
 418                 outw(val, chip->addr + offset);
 419 }
 420
 421 /*
 422  *  Basic I/O
 423  */
 424
 425 /*
 426  * access to AC97 codec via normal i/o (for ICH and SIS7013)
 427  */
 428
 429 /* return the GLOB_STA bit for the corresponding codec */
 430 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 431 {
 432         static unsigned int codec_bit[3] = {
 433                 ICH_PCR, ICH_SCR, ICH_TCR
 434         };
 435         snd_assert(codec < 3, return ICH_PCR);
 436         return codec_bit[codec];
 437 }
 438
 439 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 440 {
 441         int time;
 442
 443         if (codec > 1)
 444                 return -EIO;
 445         codec = get_ich_codec_bit(chip, codec);
 446
 447         /* codec ready ? */
 448         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 449                 return -EIO;
 450
 451         /* Anyone holding a semaphore for 1 msec should be shot... */
 452         time = 100;
 453         do {
 454                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 455                         return 0;
 456                 udelay(10);
 457         } while (time--);
 458
 459         /* access to some forbidden (non existant) ac97 registers will not
 460          * reset the semaphore. So even if you don't get the semaphore, still
 461          * continue the access. We don't need the semaphore anyway. */
 462         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 463                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 464         iagetword(chip, 0);     /* clear semaphore flag */
 465         /* I don't care about the semaphore */
 466         return -EBUSY;
 467 }
 468
 469 static void snd_intel8x0_codec_write(ac97_t *ac97,
 470                                      unsigned short reg,
 471                                      unsigned short val)
 472 {
 473         intel8x0_t *chip = ac97->private_data;
 474
 475         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 476                 if (! chip->in_ac97_init)
 477                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 478         }
 479         iaputword(chip, reg + ac97->num * 0x80, val);
 480 }
 481
 482 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 483                                               unsigned short reg)
 484 {
 485         intel8x0_t *chip = ac97->private_data;
 486         unsigned short res;
 487         unsigned int tmp;
 488
 489         if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
 490                 if (! chip->in_ac97_init)
 491                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 492                 res = 0xffff;
 493         } else {
 494                 res = iagetword(chip, reg + ac97->num * 0x80);
 495                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 496                         /* reset RCS and preserve other R/WC bits */
 497                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 498                         if (! chip->in_ac97_init)
 499                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 500                         res = 0xffff;
 501                 }
 502         }
 503         if (reg == AC97_GPIO_STATUS)
 504                 iagetword(chip, 0); /* clear semaphore */
 505         return res;
 506 }
 507
 508
 509 /*
 510  * DMA I/O
 511  */
 512 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 513 {
 514         int idx;
 515         u32 *bdbar = ichdev->bdbar;
 516         unsigned long port = ichdev->reg_offset;
 517
 518         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 519         if (ichdev->size == ichdev->fragsize) {
 520                 ichdev->ack_reload = ichdev->ack = 2;
 521                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 522                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 523                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 524                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 525                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 526                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 527                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 528                                                      ichdev->fragsize1 >> chip->pcm_pos_shift);
 529                 }
 530                 ichdev->frags = 2;
 531         } else {
 532                 ichdev->ack_reload = ichdev->ack = 1;
 533                 ichdev->fragsize1 = ichdev->fragsize;
 534                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 535                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 536                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 537                                                      ichdev->fragsize >> chip->pcm_pos_shift);
 538                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 539                 }
 540                 ichdev->frags = ichdev->size / ichdev->fragsize;
 541         }
 542         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 543         ichdev->civ = 0;
 544         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 545         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 546         ichdev->position = 0;
 547 #if 0
 548         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 549                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 550 #endif
 551         /* clear interrupts */
 552         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 553 }
 554
 555 /*
 556  *  Interrupt handler
 557  */
 558
 559 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 560 {
 561         unsigned long port = ichdev->reg_offset;
 562         int civ, i, step;
 563         int ack = 0;
 564
 565         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 566         if (civ == ichdev->civ) {
 567                 // snd_printd("civ same %d\n", civ);
 568                 step = 1;
 569                 ichdev->civ++;
 570                 ichdev->civ &= ICH_REG_LVI_MASK;
 571         } else {
 572                 step = civ - ichdev->civ;
 573                 if (step < 0)
 574                         step += ICH_REG_LVI_MASK + 1;
 575                 // if (step != 1)
 576                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 577                 ichdev->civ = civ;
 578         }
 579
 580         ichdev->position += step * ichdev->fragsize1;
 581         ichdev->position %= ichdev->size;
 582         ichdev->lvi += step;
 583         ichdev->lvi &= ICH_REG_LVI_MASK;
 584         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 585         for (i = 0; i < step; i++) {
 586                 ichdev->lvi_frag++;
 587                 ichdev->lvi_frag %= ichdev->frags;
 588                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 589         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 590                 if (--ichdev->ack == 0) {
 591                         ichdev->ack = ichdev->ack_reload;
 592                         ack = 1;
 593                 }
 594         }
 595         if (ack && ichdev->substream) {
 596                 spin_unlock(&chip->reg_lock);
 597                 snd_pcm_period_elapsed(ichdev->substream);
 598                 spin_lock(&chip->reg_lock);
 599         }
 600         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 601 }
 602
 603 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 604 {
 605         intel8x0_t *chip = dev_id;
 606         ichdev_t *ichdev;
 607         unsigned int status;
 608         unsigned int i;
 609
 610         spin_lock(&chip->reg_lock);
 611         status = igetdword(chip, chip->int_sta_reg);
 612         if (status == 0xffffffff) { /* we are not yet resumed */
 613                 spin_unlock(&chip->reg_lock);
 614                 return IRQ_NONE;
 615         }
 616         if ((status & chip->int_sta_mask) == 0) {
 617                 if (status)
 618                         iputdword(chip, chip->int_sta_reg, status);
 619                 spin_unlock(&chip->reg_lock);
 620                 return IRQ_NONE;
 621         }
 622
 623         for (i = 0; i < chip->bdbars_count; i++) {
 624                 ichdev = &chip->ichd[i];
 625                 if (status & ichdev->int_sta_mask)
 626                         snd_intel8x0_update(chip, ichdev);
 627         }
 628
 629         /* ack them */
 630         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 631         spin_unlock(&chip->reg_lock);
 632
 633         return IRQ_HANDLED;
 634 }
 635
 636 /*
 637  *  PCM part
 638  */
 639
 640 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 641 {
 642         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 643         ichdev_t *ichdev = get_ichdev(substream);
 644         unsigned char val = 0;
 645         unsigned long port = ichdev->reg_offset;
 646
 647         switch (cmd) {
 648         case SNDRV_PCM_TRIGGER_START:
 649         case SNDRV_PCM_TRIGGER_RESUME:
 650                 val = ICH_IOCE | ICH_STARTBM;
 651                 break;
 652         case SNDRV_PCM_TRIGGER_STOP:
 653         case SNDRV_PCM_TRIGGER_SUSPEND:
 654                 val = 0;
 655                 break;
 656         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 657                 val = ICH_IOCE;
 658                 break;
 659         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 660                 val = ICH_IOCE | ICH_STARTBM;
 661                 break;
 662         default:
 663                 return -EINVAL;
 664         }
 665         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 666         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 667                 /* wait until DMA stopped */
 668                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 669                 /* reset whole DMA things */
 670                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 671         }
 672         return 0;
 673 }
 674
 675 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 676                                   snd_pcm_hw_params_t * hw_params)
 677 {
 678         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 679 }
 680
 681 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 682 {
 683         return snd_pcm_lib_free_pages(substream);
 684 }
 685
 686 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
 687 {
 688         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 689         ichdev_t *ichdev = get_ichdev(substream);
 690         size_t ptr1, ptr;
 691
 692         ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
 693         if (ptr1 != 0)
 694                 ptr = ichdev->fragsize1 - ptr1;
 695         else
 696                 ptr = 0;
 697         ptr += ichdev->position;
 698         if (ptr >= ichdev->size)
 699                 return 0;
 700         return bytes_to_frames(substream->runtime, ptr);
 701 }
 702
 703 static int snd_intel8x0m_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 704 {
 705         /* hook off/on on start/stop */
 706         /* Moved this to mixer control */
 707         switch (cmd) {
 708         case SNDRV_PCM_TRIGGER_START:
 709                 break;
 710         case SNDRV_PCM_TRIGGER_STOP:
 711                 break;
 712         default:
 713                 return -EINVAL;
 714         }
 715         return snd_intel8x0_pcm_trigger(substream,cmd);
 716 }
 717
 718 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream)
 719 {
 720         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 721         snd_pcm_runtime_t *runtime = substream->runtime;
 722         ichdev_t *ichdev = get_ichdev(substream);
 723
 724         ichdev->physbuf = runtime->dma_addr;
 725         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
 726         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
 727         snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
 728         snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
 729         snd_intel8x0_setup_periods(chip, ichdev);
 730         return 0;
 731 }
 732
 733 static snd_pcm_hardware_t snd_intel8x0m_stream =
 734 {
 735         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 736                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 737                                  SNDRV_PCM_INFO_MMAP_VALID |
 738                                  SNDRV_PCM_INFO_PAUSE |
 739                                  SNDRV_PCM_INFO_RESUME),
 740         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 741         .rates =                SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
 742         .rate_min =             8000,
 743         .rate_max =             16000,
 744         .channels_min =         1,
 745         .channels_max =         1,
 746         .buffer_bytes_max =     64 * 1024,
 747         .period_bytes_min =     32,
 748         .period_bytes_max =     64 * 1024,
 749         .periods_min =          1,
 750         .periods_max =          1024,
 751         .fifo_size =            0,
 752 };
 753
 754
 755 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
 756 {
 757         static unsigned int rates[] = { 8000,  9600, 12000, 16000 };
 758         static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
 759                 .count = ARRAY_SIZE(rates),
 760                 .list = rates,
 761                 .mask = 0,
 762         };
 763         snd_pcm_runtime_t *runtime = substream->runtime;
 764         int err;
 765
 766         ichdev->substream = substream;
 767         runtime->hw = snd_intel8x0m_stream;
 768         err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
 769         if ( err < 0 )
 770                 return err;
 771         runtime->private_data = ichdev;
 772         return 0;
 773 }
 774
 775 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream)
 776 {
 777         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 778
 779         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
 780 }
 781
 782 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream)
 783 {
 784         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 785
 786         chip->ichd[ICHD_MDMOUT].substream = NULL;
 787         return 0;
 788 }
 789
 790 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream)
 791 {
 792         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 793
 794         return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
 795 }
 796
 797 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream)
 798 {
 799         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 800
 801         chip->ichd[ICHD_MDMIN].substream = NULL;
 802         return 0;
 803 }
 804
 805
 806 static snd_pcm_ops_t snd_intel8x0m_playback_ops = {
 807         .open =         snd_intel8x0m_playback_open,
 808         .close =        snd_intel8x0m_playback_close,
 809         .ioctl =        snd_pcm_lib_ioctl,
 810         .hw_params =    snd_intel8x0_hw_params,
 811         .hw_free =      snd_intel8x0_hw_free,
 812         .prepare =      snd_intel8x0m_pcm_prepare,
 813         .trigger =      snd_intel8x0m_pcm_trigger,
 814         .pointer =      snd_intel8x0_pcm_pointer,
 815 };
 816
 817 static snd_pcm_ops_t snd_intel8x0m_capture_ops = {
 818         .open =         snd_intel8x0m_capture_open,
 819         .close =        snd_intel8x0m_capture_close,
 820         .ioctl =        snd_pcm_lib_ioctl,
 821         .hw_params =    snd_intel8x0_hw_params,
 822         .hw_free =      snd_intel8x0_hw_free,
 823         .prepare =      snd_intel8x0m_pcm_prepare,
 824         .trigger =      snd_intel8x0m_pcm_trigger,
 825         .pointer =      snd_intel8x0_pcm_pointer,
 826 };
 827
 828
 829 struct ich_pcm_table {
 830         char *suffix;
 831         snd_pcm_ops_t *playback_ops;
 832         snd_pcm_ops_t *capture_ops;
 833         size_t prealloc_size;
 834         size_t prealloc_max_size;
 835         int ac97_idx;
 836 };
 837
 838 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
 839 {
 840         snd_pcm_t *pcm;
 841         int err;
 842         char name[32];
 843
 844         if (rec->suffix)
 845                 sprintf(name, "Intel ICH - %s", rec->suffix);
 846         else
 847                 strcpy(name, "Intel ICH");
 848         err = snd_pcm_new(chip->card, name, device,
 849                           rec->playback_ops ? 1 : 0,
 850                           rec->capture_ops ? 1 : 0, &pcm);
 851         if (err < 0)
 852                 return err;
 853
 854         if (rec->playback_ops)
 855                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
 856         if (rec->capture_ops)
 857                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
 858
 859         pcm->private_data = chip;
 860         pcm->info_flags = 0;
 861         if (rec->suffix)
 862                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
 863         else
 864                 strcpy(pcm->name, chip->card->shortname);
 865         chip->pcm[device] = pcm;
 866
 867         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 868                                               snd_dma_pci_data(chip->pci),
 869                                               rec->prealloc_size,
 870                                               rec->prealloc_max_size);
 871
 872         return 0;
 873 }
 874
 875 static struct ich_pcm_table intel_pcms[] __devinitdata = {
 876         {
 877                 .suffix = "Modem",
 878                 .playback_ops = &snd_intel8x0m_playback_ops,
 879                 .capture_ops = &snd_intel8x0m_capture_ops,
 880                 .prealloc_size = 32 * 1024,
 881                 .prealloc_max_size = 64 * 1024,
 882         },
 883 };
 884
 885 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
 886 {
 887         int i, tblsize, device, err;
 888         struct ich_pcm_table *tbl, *rec;
 889
 890 #if 1
 891         tbl = intel_pcms;
 892         tblsize = 1;
 893 #else
 894         switch (chip->device_type) {
 895         case DEVICE_NFORCE:
 896                 tbl = nforce_pcms;
 897                 tblsize = ARRAY_SIZE(nforce_pcms);
 898                 break;
 899         case DEVICE_ALI:
 900                 tbl = ali_pcms;
 901                 tblsize = ARRAY_SIZE(ali_pcms);
 902                 break;
 903         default:
 904                 tbl = intel_pcms;
 905                 tblsize = 2;
 906                 break;
 907         }
 908 #endif
 909         device = 0;
 910         for (i = 0; i < tblsize; i++) {
 911                 rec = tbl + i;
 912                 if (i > 0 && rec->ac97_idx) {
 913                         /* activate PCM only when associated AC'97 codec */
 914                         if (! chip->ichd[rec->ac97_idx].ac97)
 915                                 continue;
 916                 }
 917                 err = snd_intel8x0_pcm1(chip, device, rec);
 918                 if (err < 0)
 919                         return err;
 920                 device++;
 921         }
 922
 923         chip->pcm_devs = device;
 924         return 0;
 925 }
 926
 927
 928 /*
 929  *  Mixer part
 930  */
 931
 932 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
 933 {
 934         intel8x0_t *chip = bus->private_data;
 935         chip->ac97_bus = NULL;
 936 }
 937
 938 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
 939 {
 940         intel8x0_t *chip = ac97->private_data;
 941         chip->ac97 = NULL;
 942 }
 943
 944
 945 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock)
 946 {
 947         ac97_bus_t *pbus;
 948         ac97_template_t ac97;
 949         ac97_t *x97;
 950         int err;
 951         unsigned int glob_sta = 0;
 952         unsigned int idx;
 953         static ac97_bus_ops_t ops = {
 954                 .write = snd_intel8x0_codec_write,
 955                 .read = snd_intel8x0_codec_read,
 956         };
 957
 958         chip->in_ac97_init = 1;
 959
 960         memset(&ac97, 0, sizeof(ac97));
 961         ac97.private_data = chip;
 962         ac97.private_free = snd_intel8x0_mixer_free_ac97;
 963         ac97.scaps = AC97_SCAP_SKIP_AUDIO;
 964
 965         glob_sta = igetdword(chip, ICHREG(GLOB_STA));
 966
 967         if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
 968                 goto __err;
 969         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
 970         pbus->shared_type = AC97_SHARED_TYPE_ICH;       /* shared with audio driver */
 971         if (ac97_clock >= 8000 && ac97_clock <= 48000)
 972                 pbus->clock = ac97_clock;
 973         chip->ac97_bus = pbus;
 974
 975         ac97.pci = chip->pci;
 976         ac97.num = glob_sta & ICH_SCR ? 1 : 0;
 977         if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
 978                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
 979                 if (ac97.num == 0)
 980                         goto __err;
 981                 return err;
 982         }
 983         chip->ac97 = x97;
 984         if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
 985                 chip->ichd[ICHD_MDMIN].ac97 = x97;
 986                 chip->ichd[ICHD_MDMOUT].ac97 = x97;
 987         }
 988         for (idx = 0; idx < ARRAY_SIZE(snd_intel8x0m_mixer_switches); idx++) {
 989                 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_intel8x0m_mixer_switches[idx], chip))) < 0)
 990                         goto __err;
 991         }
 992
 993         chip->in_ac97_init = 0;
 994         return 0;
 995
 996  __err:
 997         /* clear the cold-reset bit for the next chance */
 998         if (chip->device_type != DEVICE_ALI)
 999                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
1000         return err;
1001 }
1002
1003
1004 /*
1005  *
1006  */
1007
1008 #define do_delay(chip) do {\
1009         set_current_state(TASK_UNINTERRUPTIBLE);\
1010         schedule_timeout(1);\
1011 } while (0)
1012
1013 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing)
1014 {
1015         unsigned long end_time;
1016         unsigned int cnt, status, nstatus;
1017
1018         /* put logic to right state */
1019         /* first clear status bits */
1020         status = ICH_RCS | ICH_MIINT | ICH_MOINT;
1021         cnt = igetdword(chip, ICHREG(GLOB_STA));
1022         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
1023
1024         /* ACLink on, 2 channels */
1025         cnt = igetdword(chip, ICHREG(GLOB_CNT));
1026         cnt &= ~(ICH_ACLINK);
1027         /* finish cold or do warm reset */
1028         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
1029         iputdword(chip, ICHREG(GLOB_CNT), cnt);
1030         end_time = (jiffies + (HZ / 4)) + 1;
1031         do {
1032                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
1033                         goto __ok;
1034                 do_delay(chip);
1035         } while (time_after_eq(end_time, jiffies));
1036         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
1037         return -EIO;
1038
1039       __ok:
1040         if (probing) {
1041                 /* wait for any codec ready status.
1042                  * Once it becomes ready it should remain ready
1043                  * as long as we do not disable the ac97 link.
1044                  */
1045                 end_time = jiffies + HZ;
1046                 do {
1047                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1048                         if (status)
1049                                 break;
1050                         do_delay(chip);
1051                 } while (time_after_eq(end_time, jiffies));
1052                 if (! status) {
1053                         /* no codec is found */
1054                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
1055                         return -EIO;
1056                 }
1057
1058                 /* up to two codecs (modem cannot be tertiary with ICH4) */
1059                 nstatus = ICH_PCR | ICH_SCR;
1060
1061                 /* wait for other codecs ready status. */
1062                 end_time = jiffies + HZ / 4;
1063                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
1064                         do_delay(chip);
1065                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
1066                 }
1067
1068         } else {
1069                 /* resume phase */
1070                 status = 0;
1071                 if (chip->ac97)
1072                         status |= get_ich_codec_bit(chip, chip->ac97->num);
1073                 /* wait until all the probed codecs are ready */
1074                 end_time = jiffies + HZ;
1075                 do {
1076                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
1077                         if (status == nstatus)
1078                                 break;
1079                         do_delay(chip);
1080                 } while (time_after_eq(end_time, jiffies));
1081         }
1082
1083         if (chip->device_type == DEVICE_SIS) {
1084                 /* unmute the output on SIS7012 */
1085                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
1086         }
1087
1088         return 0;
1089 }
1090
1091 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
1092 {
1093         unsigned int i;
1094         int err;
1095
1096         if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
1097                 return err;
1098         iagetword(chip, 0);     /* clear semaphore flag */
1099
1100         /* disable interrupts */
1101         for (i = 0; i < chip->bdbars_count; i++)
1102                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1103         /* reset channels */
1104         for (i = 0; i < chip->bdbars_count; i++)
1105                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1106         /* initialize Buffer Descriptor Lists */
1107         for (i = 0; i < chip->bdbars_count; i++)
1108                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
1109         return 0;
1110 }
1111
1112 static int snd_intel8x0_free(intel8x0_t *chip)
1113 {
1114         unsigned int i;
1115
1116         if (chip->irq < 0)
1117                 goto __hw_end;
1118         /* disable interrupts */
1119         for (i = 0; i < chip->bdbars_count; i++)
1120                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
1121         /* reset channels */
1122         for (i = 0; i < chip->bdbars_count; i++)
1123                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
1124         /* --- */
1125         synchronize_irq(chip->irq);
1126       __hw_end:
1127         if (chip->bdbars.area)
1128                 snd_dma_free_pages(&chip->bdbars);
1129         if (chip->remap_addr)
1130                 iounmap(chip->remap_addr);
1131         if (chip->remap_bmaddr)
1132                 iounmap(chip->remap_bmaddr);
1133         if (chip->irq >= 0)
1134                 free_irq(chip->irq, (void *)chip);
1135         pci_release_regions(chip->pci);
1136         pci_disable_device(chip->pci);
1137         kfree(chip);
1138         return 0;
1139 }
1140
1141 #ifdef CONFIG_PM
1142 /*
1143  * power management
1144  */
1145 static int intel8x0m_suspend(snd_card_t *card, pm_message_t state)
1146 {
1147         intel8x0_t *chip = card->pm_private_data;
1148         int i;
1149
1150         for (i = 0; i < chip->pcm_devs; i++)
1151                 snd_pcm_suspend_all(chip->pcm[i]);
1152         if (chip->ac97)
1153                 snd_ac97_suspend(chip->ac97);
1154         pci_disable_device(chip->pci);
1155         return 0;
1156 }
1157
1158 static int intel8x0m_resume(snd_card_t *card)
1159 {
1160         intel8x0_t *chip = card->pm_private_data;
1161         pci_enable_device(chip->pci);
1162         pci_set_master(chip->pci);
1163         snd_intel8x0_chip_init(chip, 0);
1164         if (chip->ac97)
1165                 snd_ac97_resume(chip->ac97);
1166
1167         return 0;
1168 }
1169 #endif /* CONFIG_PM */
1170
1171 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry,
1172                                    snd_info_buffer_t * buffer)
1173 {
1174         intel8x0_t *chip = entry->private_data;
1175         unsigned int tmp;
1176
1177         snd_iprintf(buffer, "Intel8x0m\n\n");
1178         if (chip->device_type == DEVICE_ALI)
1179                 return;
1180         tmp = igetdword(chip, ICHREG(GLOB_STA));
1181         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
1182         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
1183         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
1184                         tmp & ICH_PCR ? " primary" : "",
1185                         tmp & ICH_SCR ? " secondary" : "",
1186                         tmp & ICH_TCR ? " tertiary" : "",
1187                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1188 }
1189
1190 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip)
1191 {
1192         snd_info_entry_t *entry;
1193
1194         if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1195                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read);
1196 }
1197
1198 static int snd_intel8x0_dev_free(snd_device_t *device)
1199 {
1200         intel8x0_t *chip = device->device_data;
1201         return snd_intel8x0_free(chip);
1202 }
1203
1204 struct ich_reg_info {
1205         unsigned int int_sta_mask;
1206         unsigned int offset;
1207 };
1208
1209 static int __devinit snd_intel8x0m_create(snd_card_t * card,
1210                                          struct pci_dev *pci,
1211                                          unsigned long device_type,
1212                                          intel8x0_t ** r_intel8x0)
1213 {
1214         intel8x0_t *chip;
1215         int err;
1216         unsigned int i;
1217         unsigned int int_sta_masks;
1218         ichdev_t *ichdev;
1219         static snd_device_ops_t ops = {
1220                 .dev_free =     snd_intel8x0_dev_free,
1221         };
1222         static struct ich_reg_info intel_regs[2] = {
1223                 { ICH_MIINT, 0 },
1224                 { ICH_MOINT, 0x10 },
1225         };
1226         struct ich_reg_info *tbl;
1227
1228         *r_intel8x0 = NULL;
1229
1230         if ((err = pci_enable_device(pci)) < 0)
1231                 return err;
1232
1233         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1234         if (chip == NULL) {
1235                 pci_disable_device(pci);
1236                 return -ENOMEM;
1237         }
1238         spin_lock_init(&chip->reg_lock);
1239         chip->device_type = device_type;
1240         chip->card = card;
1241         chip->pci = pci;
1242         chip->irq = -1;
1243
1244         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1245                 kfree(chip);
1246                 pci_disable_device(pci);
1247                 return err;
1248         }
1249
1250         if (device_type == DEVICE_ALI) {
1251                 /* ALI5455 has no ac97 region */
1252                 chip->bmaddr = pci_resource_start(pci, 0);
1253                 goto port_inited;
1254         }
1255
1256         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
1257                 chip->mmio = 1;
1258                 chip->addr = pci_resource_start(pci, 2);
1259                 chip->remap_addr = ioremap_nocache(chip->addr,
1260                                                    pci_resource_len(pci, 2));
1261                 if (chip->remap_addr == NULL) {
1262                         snd_printk("AC'97 space ioremap problem\n");
1263                         snd_intel8x0_free(chip);
1264                         return -EIO;
1265                 }
1266         } else {
1267                 chip->addr = pci_resource_start(pci, 0);
1268         }
1269         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
1270                 chip->bm_mmio = 1;
1271                 chip->bmaddr = pci_resource_start(pci, 3);
1272                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
1273                                                      pci_resource_len(pci, 3));
1274                 if (chip->remap_bmaddr == NULL) {
1275                         snd_printk("Controller space ioremap problem\n");
1276                         snd_intel8x0_free(chip);
1277                         return -EIO;
1278                 }
1279         } else {
1280                 chip->bmaddr = pci_resource_start(pci, 1);
1281         }
1282
1283  port_inited:
1284         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1285                 snd_printk("unable to grab IRQ %d\n", pci->irq);
1286                 snd_intel8x0_free(chip);
1287                 return -EBUSY;
1288         }
1289         chip->irq = pci->irq;
1290         pci_set_master(pci);
1291         synchronize_irq(chip->irq);
1292
1293         /* initialize offsets */
1294         chip->bdbars_count = 2;
1295         tbl = intel_regs;
1296
1297         for (i = 0; i < chip->bdbars_count; i++) {
1298                 ichdev = &chip->ichd[i];
1299                 ichdev->ichd = i;
1300                 ichdev->reg_offset = tbl[i].offset;
1301                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
1302                 if (device_type == DEVICE_SIS) {
1303                         /* SiS 7013 swaps the registers */
1304                         ichdev->roff_sr = ICH_REG_OFF_PICB;
1305                         ichdev->roff_picb = ICH_REG_OFF_SR;
1306                 } else {
1307                         ichdev->roff_sr = ICH_REG_OFF_SR;
1308                         ichdev->roff_picb = ICH_REG_OFF_PICB;
1309                 }
1310                 if (device_type == DEVICE_ALI)
1311                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1312         }
1313         /* SIS7013 handles the pcm data in bytes, others are in words */
1314         chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1315
1316         /* allocate buffer descriptor lists */
1317         /* the start of each lists must be aligned to 8 bytes */
1318         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1319                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1320                                 &chip->bdbars) < 0) {
1321                 snd_intel8x0_free(chip);
1322                 return -ENOMEM;
1323         }
1324         /* tables must be aligned to 8 bytes here, but the kernel pages
1325            are much bigger, so we don't care (on i386) */
1326         int_sta_masks = 0;
1327         for (i = 0; i < chip->bdbars_count; i++) {
1328                 ichdev = &chip->ichd[i];
1329                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1330                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1331                 int_sta_masks |= ichdev->int_sta_mask;
1332         }
1333         chip->int_sta_reg = ICH_REG_GLOB_STA;
1334         chip->int_sta_mask = int_sta_masks;
1335
1336         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1337                 snd_intel8x0_free(chip);
1338                 return err;
1339         }
1340
1341         snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip);
1342
1343         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1344                 snd_intel8x0_free(chip);
1345                 return err;
1346         }
1347
1348         snd_card_set_dev(card, &pci->dev);
1349
1350         *r_intel8x0 = chip;
1351         return 0;
1352 }
1353
1354 static struct shortname_table {
1355         unsigned int id;
1356         const char *s;
1357 } shortnames[] __devinitdata = {
1358         { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" },
1359         { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" },
1360         { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1361         { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1362         { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" },
1363         { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" },
1364         { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" },
1365         { PCI_DEVICE_ID_INTEL_ICH6_6, "Intel ICH6" },
1366         { PCI_DEVICE_ID_INTEL_ICH7_6, "Intel ICH7" },
1367         { 0x7446, "AMD AMD768" },
1368         { PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1369         { PCI_DEVICE_ID_NVIDIA_MCP_MODEM, "NVidia nForce" },
1370         { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1371         { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1372         { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1373 #if 0
1374         { 0x5455, "ALi M5455" },
1375         { 0x746d, "AMD AMD8111" },
1376 #endif
1377         { 0 },
1378 };
1379
1380 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1381                                         const struct pci_device_id *pci_id)
1382 {
1383         static int dev;
1384         snd_card_t *card;
1385         intel8x0_t *chip;
1386         int err;
1387         struct shortname_table *name;
1388
1389         if (dev >= SNDRV_CARDS)
1390                 return -ENODEV;
1391         if (!enable[dev]) {
1392                 dev++;
1393                 return -ENOENT;
1394         }
1395
1396         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1397         if (card == NULL)
1398                 return -ENOMEM;
1399
1400         strcpy(card->driver, "ICH-MODEM");
1401         strcpy(card->shortname, "Intel ICH");
1402         for (name = shortnames; name->id; name++) {
1403                 if (pci->device == name->id) {
1404                         strcpy(card->shortname, name->s);
1405                         break;
1406                 }
1407         }
1408         strcat(card->shortname," Modem");
1409
1410         if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1411                 snd_card_free(card);
1412                 return err;
1413         }
1414
1415         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) {
1416                 snd_card_free(card);
1417                 return err;
1418         }
1419         if ((err = snd_intel8x0_pcm(chip)) < 0) {
1420                 snd_card_free(card);
1421                 return err;
1422         }
1423
1424         snd_intel8x0m_proc_init(chip);
1425
1426         sprintf(card->longname, "%s at 0x%lx, irq %i",
1427                 card->shortname, chip->addr, chip->irq);
1428
1429         if ((err = snd_card_register(card)) < 0) {
1430                 snd_card_free(card);
1431                 return err;
1432         }
1433         pci_set_drvdata(pci, card);
1434         dev++;
1435         return 0;
1436 }
1437
1438 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1439 {
1440         snd_card_free(pci_get_drvdata(pci));
1441         pci_set_drvdata(pci, NULL);
1442 }
1443
1444 static struct pci_driver driver = {
1445         .name = "Intel ICH Modem",
1446         .id_table = snd_intel8x0m_ids,
1447         .probe = snd_intel8x0m_probe,
1448         .remove = __devexit_p(snd_intel8x0m_remove),
1449         SND_PCI_PM_CALLBACKS
1450 };
1451
1452
1453 static int __init alsa_card_intel8x0m_init(void)
1454 {
1455         return pci_register_driver(&driver);
1456 }
1457
1458 static void __exit alsa_card_intel8x0m_exit(void)
1459 {
1460         pci_unregister_driver(&driver);
1461 }
1462
1463 module_init(alsa_card_intel8x0m_init)
1464 module_exit(alsa_card_intel8x0m_exit)