2 * ALSA driver for ICEnsemble ICE1724 (Envy24)
4 * Lowlevel functions for Terratec PHASE 22
6 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * Audio controller: VIA Envy24HT-S (slightly trimmed down version of Envy24HT)
26 * Analog chip: AK4524 (partially via Philip's 74HCT125)
27 * Digital receiver: CS8414-CS (not supported in this release)
29 * Envy connects to AK4524
30 * - CS directly from GPIO 10
31 * - CCLK via 74HCT125's gate #4 from GPIO 4
32 * - CDTI via 74HCT125's gate #2 from GPIO 5
33 * CDTI may be completely blocked by 74HCT125's gate #1 controlled by GPIO 3
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/init.h>
41 #include <linux/slab.h>
42 #include <linux/mutex.h>
44 #include <sound/core.h>
49 #include <sound/tlv.h>
51 /* WM8770 registers */
52 #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
53 #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
54 #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
55 #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
56 #define WM_PHASE_SWAP 0x12 /* DAC phase */
57 #define WM_DAC_CTRL1 0x13 /* DAC control bits */
58 #define WM_MUTE 0x14 /* mute controls */
59 #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
60 #define WM_INT_CTRL 0x16 /* interface control */
61 #define WM_MASTER 0x17 /* master clock and mode */
62 #define WM_POWERDOWN 0x18 /* power-down controls */
63 #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
64 #define WM_ADC_MUX 0x1b /* input MUX */
65 #define WM_OUT_MUX1 0x1c /* output MUX */
66 #define WM_OUT_MUX2 0x1e /* output MUX */
67 #define WM_RESET 0x1f /* software reset */
71 * Logarithmic volume values for WM8770
72 * Computed as 20 * Log10(255 / x)
74 static const unsigned char wm_vol[256] = {
75 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24, 24, 23,
76 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17,
77 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 13, 13, 13,
78 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11,
79 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
80 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
81 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
82 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3,
83 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
84 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
85 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
89 #define WM_VOL_MAX (sizeof(wm_vol) - 1)
90 #define WM_VOL_MUTE 0x8000
92 static struct snd_akm4xxx akm_phase22 __devinitdata = {
98 static struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
110 static int __devinit phase22_init(struct snd_ice1712 *ice)
112 struct snd_akm4xxx *ak;
115 // Configure DAC/ADC description for generic part of ice1724
116 switch (ice->eeprom.subvendor) {
117 case VT1724_SUBDEVICE_PHASE22:
118 ice->num_total_dacs = 2;
119 ice->num_total_adcs = 2;
120 ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
127 // Initialize analog chips
128 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
132 switch (ice->eeprom.subvendor) {
133 case VT1724_SUBDEVICE_PHASE22:
134 if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
142 static int __devinit phase22_add_controls(struct snd_ice1712 *ice)
146 switch (ice->eeprom.subvendor) {
147 case VT1724_SUBDEVICE_PHASE22:
148 err = snd_ice1712_akm4xxx_build_controls(ice);
155 static unsigned char phase22_eeprom[] __devinitdata = {
156 [ICE_EEP2_SYSCONF] = 0x00, /* 1xADC, 1xDACs */
157 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
158 [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit */
159 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
160 [ICE_EEP2_GPIO_DIR] = 0xff,
161 [ICE_EEP2_GPIO_DIR1] = 0xff,
162 [ICE_EEP2_GPIO_DIR2] = 0xff,
163 [ICE_EEP2_GPIO_MASK] = 0x00,
164 [ICE_EEP2_GPIO_MASK1] = 0x00,
165 [ICE_EEP2_GPIO_MASK2] = 0x00,
166 [ICE_EEP2_GPIO_STATE] = 0x00,
167 [ICE_EEP2_GPIO_STATE1] = 0x00,
168 [ICE_EEP2_GPIO_STATE2] = 0x00,
171 static unsigned char phase28_eeprom[] __devinitdata = {
172 [ICE_EEP2_SYSCONF] = 0x0b, /* clock 512, spdif-in/ADC, 4DACs */
173 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
174 [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
175 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
176 [ICE_EEP2_GPIO_DIR] = 0xff,
177 [ICE_EEP2_GPIO_DIR1] = 0xff,
178 [ICE_EEP2_GPIO_DIR2] = 0x5f,
179 [ICE_EEP2_GPIO_MASK] = 0x00,
180 [ICE_EEP2_GPIO_MASK1] = 0x00,
181 [ICE_EEP2_GPIO_MASK2] = 0x00,
182 [ICE_EEP2_GPIO_STATE] = 0x00,
183 [ICE_EEP2_GPIO_STATE1] = 0x00,
184 [ICE_EEP2_GPIO_STATE2] = 0x00,
188 * write data in the SPI mode
190 static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
195 tmp = snd_ice1712_gpio_read(ice);
197 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|PHASE28_SPI_CLK|
199 tmp |= PHASE28_WM_RW;
201 snd_ice1712_gpio_write(ice, tmp);
204 for (i = bits - 1; i >= 0; i--) {
205 tmp &= ~PHASE28_SPI_CLK;
206 snd_ice1712_gpio_write(ice, tmp);
209 tmp |= PHASE28_SPI_MOSI;
211 tmp &= ~PHASE28_SPI_MOSI;
212 snd_ice1712_gpio_write(ice, tmp);
214 tmp |= PHASE28_SPI_CLK;
215 snd_ice1712_gpio_write(ice, tmp);
219 tmp &= ~PHASE28_SPI_CLK;
221 snd_ice1712_gpio_write(ice, tmp);
223 tmp |= PHASE28_SPI_CLK;
224 snd_ice1712_gpio_write(ice, tmp);
229 * get the current register value of WM codec
231 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
234 return ((unsigned short)ice->akm[0].images[reg] << 8) |
235 ice->akm[0].images[reg + 1];
239 * set the register value of WM codec
241 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
243 phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
247 * set the register value of WM codec and remember it
249 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
251 wm_put_nocache(ice, reg, val);
253 ice->akm[0].images[reg] = val >> 8;
254 ice->akm[0].images[reg + 1] = val;
257 static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
261 if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
264 nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
266 wm_put(ice, index, nvol);
267 wm_put_nocache(ice, index, 0x180 | nvol);
273 #define wm_pcm_mute_info snd_ctl_boolean_mono_info
275 static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
277 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
279 mutex_lock(&ice->gpio_mutex);
280 ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
281 mutex_unlock(&ice->gpio_mutex);
285 static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
287 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
288 unsigned short nval, oval;
291 snd_ice1712_save_gpio_status(ice);
292 oval = wm_get(ice, WM_MUTE);
293 nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
294 if ((change = (nval != oval)))
295 wm_put(ice, WM_MUTE, nval);
296 snd_ice1712_restore_gpio_status(ice);
302 * Master volume attenuation mixer control
304 static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
306 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
308 uinfo->value.integer.min = 0;
309 uinfo->value.integer.max = WM_VOL_MAX;
313 static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
315 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
318 ucontrol->value.integer.value[i] = ice->spec.phase28.master[i] & ~WM_VOL_MUTE;
322 static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
324 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
327 snd_ice1712_save_gpio_status(ice);
328 for (ch = 0; ch < 2; ch++) {
329 unsigned int vol = ucontrol->value.integer.value[ch];
330 if (vol > WM_VOL_MAX)
332 vol |= ice->spec.phase28.master[ch] & WM_VOL_MUTE;
333 if (vol != ice->spec.phase28.master[ch]) {
335 ice->spec.phase28.master[ch] = vol;
336 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
337 wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
338 ice->spec.phase28.vol[dac + ch],
339 ice->spec.phase28.master[ch]);
343 snd_ice1712_restore_gpio_status(ice);
347 static int __devinit phase28_init(struct snd_ice1712 *ice)
349 static const unsigned short wm_inits_phase28[] = {
350 /* These come first to reduce init pop noise */
351 0x1b, 0x044, /* ADC Mux (AC'97 source) */
352 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
353 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
355 0x18, 0x000, /* All power-up */
357 0x16, 0x122, /* I2S, normal polarity, 24bit */
358 0x17, 0x022, /* 256fs, slave mode */
359 0x00, 0, /* DAC1 analog mute */
360 0x01, 0, /* DAC2 analog mute */
361 0x02, 0, /* DAC3 analog mute */
362 0x03, 0, /* DAC4 analog mute */
363 0x04, 0, /* DAC5 analog mute */
364 0x05, 0, /* DAC6 analog mute */
365 0x06, 0, /* DAC7 analog mute */
366 0x07, 0, /* DAC8 analog mute */
367 0x08, 0x100, /* master analog mute */
368 0x09, 0xff, /* DAC1 digital full */
369 0x0a, 0xff, /* DAC2 digital full */
370 0x0b, 0xff, /* DAC3 digital full */
371 0x0c, 0xff, /* DAC4 digital full */
372 0x0d, 0xff, /* DAC5 digital full */
373 0x0e, 0xff, /* DAC6 digital full */
374 0x0f, 0xff, /* DAC7 digital full */
375 0x10, 0xff, /* DAC8 digital full */
376 0x11, 0x1ff, /* master digital full */
377 0x12, 0x000, /* phase normal */
378 0x13, 0x090, /* unmute DAC L/R */
379 0x14, 0x000, /* all unmute */
380 0x15, 0x000, /* no deemphasis, no ZFLG */
381 0x19, 0x000, /* -12dB ADC/L */
382 0x1a, 0x000, /* -12dB ADC/R */
387 struct snd_akm4xxx *ak;
388 const unsigned short *p;
391 ice->num_total_dacs = 8;
392 ice->num_total_adcs = 2;
394 // Initialize analog chips
395 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
400 snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
402 /* reset the wm codec as the SPI mode */
403 snd_ice1712_save_gpio_status(ice);
404 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
406 tmp = snd_ice1712_gpio_read(ice);
407 tmp &= ~PHASE28_WM_RESET;
408 snd_ice1712_gpio_write(ice, tmp);
410 tmp |= PHASE28_WM_CS;
411 snd_ice1712_gpio_write(ice, tmp);
413 tmp |= PHASE28_WM_RESET;
414 snd_ice1712_gpio_write(ice, tmp);
417 p = wm_inits_phase28;
418 for (; *p != (unsigned short)-1; p += 2)
419 wm_put(ice, p[0], p[1]);
421 snd_ice1712_restore_gpio_status(ice);
423 ice->spec.phase28.master[0] = WM_VOL_MUTE;
424 ice->spec.phase28.master[1] = WM_VOL_MUTE;
425 for (i = 0; i < ice->num_total_dacs; i++) {
426 ice->spec.phase28.vol[i] = WM_VOL_MUTE;
427 wm_set_vol(ice, i, ice->spec.phase28.vol[i], ice->spec.phase28.master[i % 2]);
434 * DAC volume attenuation mixer control
436 static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
438 int voices = kcontrol->private_value >> 8;
439 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
440 uinfo->count = voices;
441 uinfo->value.integer.min = 0; /* mute (-101dB) */
442 uinfo->value.integer.max = 0x7F; /* 0dB */
446 static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
448 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
451 voices = kcontrol->private_value >> 8;
452 ofs = kcontrol->private_value & 0xff;
453 for (i = 0; i < voices; i++)
454 ucontrol->value.integer.value[i] = ice->spec.phase28.vol[ofs+i] & ~WM_VOL_MUTE;
458 static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
460 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
461 int i, idx, ofs, voices;
464 voices = kcontrol->private_value >> 8;
465 ofs = kcontrol->private_value & 0xff;
466 snd_ice1712_save_gpio_status(ice);
467 for (i = 0; i < voices; i++) {
469 vol = ucontrol->value.integer.value[i];
472 vol |= ice->spec.phase28.vol[ofs+i] & WM_VOL_MUTE;
473 if (vol != ice->spec.phase28.vol[ofs+i]) {
474 ice->spec.phase28.vol[ofs+i] = vol;
475 idx = WM_DAC_ATTEN + ofs + i;
476 wm_set_vol(ice, idx, ice->spec.phase28.vol[ofs+i],
477 ice->spec.phase28.master[i]);
481 snd_ice1712_restore_gpio_status(ice);
486 * WM8770 mute control
488 static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
489 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
490 uinfo->count = kcontrol->private_value >> 8;
491 uinfo->value.integer.min = 0;
492 uinfo->value.integer.max = 1;
496 static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
498 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
501 voices = kcontrol->private_value >> 8;
502 ofs = kcontrol->private_value & 0xFF;
504 for (i = 0; i < voices; i++)
505 ucontrol->value.integer.value[i] = (ice->spec.phase28.vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
509 static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
511 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
512 int change = 0, voices, ofs, i;
514 voices = kcontrol->private_value >> 8;
515 ofs = kcontrol->private_value & 0xFF;
517 snd_ice1712_save_gpio_status(ice);
518 for (i = 0; i < voices; i++) {
519 int val = (ice->spec.phase28.vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
520 if (ucontrol->value.integer.value[i] != val) {
521 ice->spec.phase28.vol[ofs + i] &= ~WM_VOL_MUTE;
522 ice->spec.phase28.vol[ofs + i] |=
523 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
524 wm_set_vol(ice, ofs + i, ice->spec.phase28.vol[ofs + i],
525 ice->spec.phase28.master[i]);
529 snd_ice1712_restore_gpio_status(ice);
535 * WM8770 master mute control
537 #define wm_master_mute_info snd_ctl_boolean_stereo_info
539 static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
541 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
543 ucontrol->value.integer.value[0] = (ice->spec.phase28.master[0] & WM_VOL_MUTE) ? 0 : 1;
544 ucontrol->value.integer.value[1] = (ice->spec.phase28.master[1] & WM_VOL_MUTE) ? 0 : 1;
548 static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
550 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
553 snd_ice1712_save_gpio_status(ice);
554 for (i = 0; i < 2; i++) {
555 int val = (ice->spec.phase28.master[i] & WM_VOL_MUTE) ? 0 : 1;
556 if (ucontrol->value.integer.value[i] != val) {
558 ice->spec.phase28.master[i] &= ~WM_VOL_MUTE;
559 ice->spec.phase28.master[i] |=
560 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
561 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
562 wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
563 ice->spec.phase28.vol[dac + i],
564 ice->spec.phase28.master[i]);
568 snd_ice1712_restore_gpio_status(ice);
573 /* digital master volume */
575 #define PCM_RES 128 /* -64dB */
576 #define PCM_MIN (PCM_0dB - PCM_RES)
577 static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
579 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
581 uinfo->value.integer.min = 0; /* mute (-64dB) */
582 uinfo->value.integer.max = PCM_RES; /* 0dB */
586 static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
588 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
591 mutex_lock(&ice->gpio_mutex);
592 val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
593 val = val > PCM_MIN ? (val - PCM_MIN) : 0;
594 ucontrol->value.integer.value[0] = val;
595 mutex_unlock(&ice->gpio_mutex);
599 static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
601 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
602 unsigned short ovol, nvol;
605 nvol = ucontrol->value.integer.value[0];
608 snd_ice1712_save_gpio_status(ice);
609 nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
610 ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
612 wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
613 wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
616 snd_ice1712_restore_gpio_status(ice);
623 #define phase28_deemp_info snd_ctl_boolean_mono_info
625 static int phase28_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
627 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
628 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
632 static int phase28_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
634 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
636 temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
637 if (ucontrol->value.integer.value[0])
642 wm_put(ice, WM_DAC_CTRL2, temp);
651 static int phase28_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
653 static char *texts[2] = { "128x", "64x" };
655 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
657 uinfo->value.enumerated.items = 2;
659 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
660 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
661 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
666 static int phase28_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
668 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
669 ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
673 static int phase28_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
676 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
678 temp2 = temp = wm_get(ice, WM_MASTER);
680 if (ucontrol->value.enumerated.item[0])
686 wm_put(ice, WM_MASTER, temp);
692 static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
693 static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
695 static struct snd_kcontrol_new phase28_dac_controls[] __devinitdata = {
697 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
698 .name = "Master Playback Switch",
699 .info = wm_master_mute_info,
700 .get = wm_master_mute_get,
701 .put = wm_master_mute_put
704 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
705 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
706 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
707 .name = "Master Playback Volume",
708 .info = wm_master_vol_info,
709 .get = wm_master_vol_get,
710 .put = wm_master_vol_put,
711 .tlv = { .p = db_scale_wm_dac }
714 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
715 .name = "Front Playback Switch",
716 .info = wm_mute_info,
719 .private_value = (2 << 8) | 0
722 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
723 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
724 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
725 .name = "Front Playback Volume",
729 .private_value = (2 << 8) | 0,
730 .tlv = { .p = db_scale_wm_dac }
733 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
734 .name = "Rear Playback Switch",
735 .info = wm_mute_info,
738 .private_value = (2 << 8) | 2
741 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
742 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
743 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
744 .name = "Rear Playback Volume",
748 .private_value = (2 << 8) | 2,
749 .tlv = { .p = db_scale_wm_dac }
752 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
753 .name = "Center Playback Switch",
754 .info = wm_mute_info,
757 .private_value = (1 << 8) | 4
760 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
761 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
762 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
763 .name = "Center Playback Volume",
767 .private_value = (1 << 8) | 4,
768 .tlv = { .p = db_scale_wm_dac }
771 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
772 .name = "LFE Playback Switch",
773 .info = wm_mute_info,
776 .private_value = (1 << 8) | 5
779 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
780 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
781 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
782 .name = "LFE Playback Volume",
786 .private_value = (1 << 8) | 5,
787 .tlv = { .p = db_scale_wm_dac }
790 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
791 .name = "Side Playback Switch",
792 .info = wm_mute_info,
795 .private_value = (2 << 8) | 6
798 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
799 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
800 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
801 .name = "Side Playback Volume",
805 .private_value = (2 << 8) | 6,
806 .tlv = { .p = db_scale_wm_dac }
810 static struct snd_kcontrol_new wm_controls[] __devinitdata = {
812 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
813 .name = "PCM Playback Switch",
814 .info = wm_pcm_mute_info,
815 .get = wm_pcm_mute_get,
816 .put = wm_pcm_mute_put
819 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
820 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
821 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
822 .name = "PCM Playback Volume",
823 .info = wm_pcm_vol_info,
824 .get = wm_pcm_vol_get,
825 .put = wm_pcm_vol_put,
826 .tlv = { .p = db_scale_wm_pcm }
829 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
830 .name = "DAC Deemphasis Switch",
831 .info = phase28_deemp_info,
832 .get = phase28_deemp_get,
833 .put = phase28_deemp_put
836 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
837 .name = "ADC Oversampling",
838 .info = phase28_oversampling_info,
839 .get = phase28_oversampling_get,
840 .put = phase28_oversampling_put
844 static int __devinit phase28_add_controls(struct snd_ice1712 *ice)
846 unsigned int i, counts;
849 counts = ARRAY_SIZE(phase28_dac_controls);
850 for (i = 0; i < counts; i++) {
851 err = snd_ctl_add(ice->card, snd_ctl_new1(&phase28_dac_controls[i], ice));
856 for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
857 err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
865 struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
867 .subvendor = VT1724_SUBDEVICE_PHASE22,
868 .name = "Terratec PHASE 22",
870 .chip_init = phase22_init,
871 .build_controls = phase22_add_controls,
872 .eeprom_size = sizeof(phase22_eeprom),
873 .eeprom_data = phase22_eeprom,
876 .subvendor = VT1724_SUBDEVICE_PHASE28,
877 .name = "Terratec PHASE 28",
879 .chip_init = phase28_init,
880 .build_controls = phase28_add_controls,
881 .eeprom_size = sizeof(phase28_eeprom),
882 .eeprom_data = phase28_eeprom,