3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <sound/driver.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
53 static int index = SNDRV_DEFAULT_IDX1;
54 static char *id = SNDRV_DEFAULT_STR1;
56 static int position_fix;
57 static int probe_mask = -1;
58 static int single_cmd;
59 static int enable_msi;
61 module_param(index, int, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param(id, charp, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param(model, charp, 0444);
66 MODULE_PARM_DESC(model, "Use the given board model.");
67 module_param(position_fix, int, 0444);
68 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
69 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
70 module_param(probe_mask, int, 0444);
71 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
72 module_param(single_cmd, bool, 0444);
73 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
74 "(for debugging only).");
75 module_param(enable_msi, int, 0);
76 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
79 /* just for backward compatibility */
81 module_param(enable, bool, 0444);
83 MODULE_LICENSE("GPL");
84 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
100 MODULE_DESCRIPTION("Intel HDA driver");
102 #define SFX "hda-intel: "
107 #define ICH6_REG_GCAP 0x00
108 #define ICH6_REG_VMIN 0x02
109 #define ICH6_REG_VMAJ 0x03
110 #define ICH6_REG_OUTPAY 0x04
111 #define ICH6_REG_INPAY 0x06
112 #define ICH6_REG_GCTL 0x08
113 #define ICH6_REG_WAKEEN 0x0c
114 #define ICH6_REG_STATESTS 0x0e
115 #define ICH6_REG_GSTS 0x10
116 #define ICH6_REG_INTCTL 0x20
117 #define ICH6_REG_INTSTS 0x24
118 #define ICH6_REG_WALCLK 0x30
119 #define ICH6_REG_SYNC 0x34
120 #define ICH6_REG_CORBLBASE 0x40
121 #define ICH6_REG_CORBUBASE 0x44
122 #define ICH6_REG_CORBWP 0x48
123 #define ICH6_REG_CORBRP 0x4A
124 #define ICH6_REG_CORBCTL 0x4c
125 #define ICH6_REG_CORBSTS 0x4d
126 #define ICH6_REG_CORBSIZE 0x4e
128 #define ICH6_REG_RIRBLBASE 0x50
129 #define ICH6_REG_RIRBUBASE 0x54
130 #define ICH6_REG_RIRBWP 0x58
131 #define ICH6_REG_RINTCNT 0x5a
132 #define ICH6_REG_RIRBCTL 0x5c
133 #define ICH6_REG_RIRBSTS 0x5d
134 #define ICH6_REG_RIRBSIZE 0x5e
136 #define ICH6_REG_IC 0x60
137 #define ICH6_REG_IR 0x64
138 #define ICH6_REG_IRS 0x68
139 #define ICH6_IRS_VALID (1<<1)
140 #define ICH6_IRS_BUSY (1<<0)
142 #define ICH6_REG_DPLBASE 0x70
143 #define ICH6_REG_DPUBASE 0x74
144 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
146 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
147 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
149 /* stream register offsets from stream base */
150 #define ICH6_REG_SD_CTL 0x00
151 #define ICH6_REG_SD_STS 0x03
152 #define ICH6_REG_SD_LPIB 0x04
153 #define ICH6_REG_SD_CBL 0x08
154 #define ICH6_REG_SD_LVI 0x0c
155 #define ICH6_REG_SD_FIFOW 0x0e
156 #define ICH6_REG_SD_FIFOSIZE 0x10
157 #define ICH6_REG_SD_FORMAT 0x12
158 #define ICH6_REG_SD_BDLPL 0x18
159 #define ICH6_REG_SD_BDLPU 0x1c
162 #define ICH6_PCIREG_TCSEL 0x44
168 /* max number of SDs */
169 /* ICH, ATI and VIA have 4 playback and 4 capture */
170 #define ICH6_CAPTURE_INDEX 0
171 #define ICH6_NUM_CAPTURE 4
172 #define ICH6_PLAYBACK_INDEX 4
173 #define ICH6_NUM_PLAYBACK 4
175 /* ULI has 6 playback and 5 capture */
176 #define ULI_CAPTURE_INDEX 0
177 #define ULI_NUM_CAPTURE 5
178 #define ULI_PLAYBACK_INDEX 5
179 #define ULI_NUM_PLAYBACK 6
181 /* ATI HDMI has 1 playback and 0 capture */
182 #define ATIHDMI_CAPTURE_INDEX 0
183 #define ATIHDMI_NUM_CAPTURE 0
184 #define ATIHDMI_PLAYBACK_INDEX 0
185 #define ATIHDMI_NUM_PLAYBACK 1
187 /* this number is statically defined for simplicity */
188 #define MAX_AZX_DEV 16
190 /* max number of fragments - we may use more if allocating more pages for BDL */
191 #define BDL_SIZE PAGE_ALIGN(8192)
192 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
193 /* max buffer size - no h/w limit, you can increase as you like */
194 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
195 /* max number of PCM devics per card */
196 #define AZX_MAX_AUDIO_PCMS 6
197 #define AZX_MAX_MODEM_PCMS 2
198 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
200 /* RIRB int mask: overrun[2], response[0] */
201 #define RIRB_INT_RESPONSE 0x01
202 #define RIRB_INT_OVERRUN 0x04
203 #define RIRB_INT_MASK 0x05
205 /* STATESTS int mask: SD2,SD1,SD0 */
206 #define AZX_MAX_CODECS 3
207 #define STATESTS_INT_MASK 0x07
210 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
211 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
212 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
213 #define SD_CTL_STREAM_TAG_SHIFT 20
215 /* SD_CTL and SD_STS */
216 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
217 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
218 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
219 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
223 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
225 /* INTCTL and INTSTS */
226 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
227 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
228 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
230 /* GCTL unsolicited response enable bit */
231 #define ICH6_GCTL_UREN (1<<8)
234 #define ICH6_GCTL_RESET (1<<0)
236 /* CORB/RIRB control, read/write pointer */
237 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
238 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
239 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
240 /* below are so far hardcoded - should read registers in future */
241 #define ICH6_MAX_CORB_ENTRIES 256
242 #define ICH6_MAX_RIRB_ENTRIES 256
244 /* position fix mode */
252 /* Defines for ATI HD Audio support in SB450 south bridge */
253 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
254 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
256 /* Defines for Nvidia HDA support */
257 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
258 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
264 u32 *bdl; /* virtual address of the BDL */
265 dma_addr_t bdl_addr; /* physical address of the BDL */
266 u32 *posbuf; /* position buffer pointer */
268 unsigned int bufsize; /* size of the play buffer in bytes */
269 unsigned int fragsize; /* size of each period in bytes */
270 unsigned int frags; /* number for period in the play buffer */
271 unsigned int fifo_size; /* FIFO size */
273 void __iomem *sd_addr; /* stream descriptor pointer */
275 u32 sd_int_sta_mask; /* stream int status mask */
278 struct snd_pcm_substream *substream; /* assigned substream,
281 unsigned int format_val; /* format value to be set in the
282 * controller and the codec
284 unsigned char stream_tag; /* assigned stream */
285 unsigned char index; /* stream index */
286 /* for sanity check of position buffer */
287 unsigned int period_intr;
289 unsigned int opened :1;
290 unsigned int running :1;
295 u32 *buf; /* CORB/RIRB buffer
296 * Each CORB entry is 4byte, RIRB is 8byte
298 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
300 unsigned short rp, wp; /* read/write pointers */
301 int cmds; /* number of pending requests */
302 u32 res; /* last read value */
306 struct snd_card *card;
309 /* chip type specific */
311 int playback_streams;
312 int playback_index_offset;
314 int capture_index_offset;
319 void __iomem *remap_addr;
324 struct mutex open_mutex;
326 /* streams (x num_streams) */
327 struct azx_dev *azx_dev;
330 unsigned int pcm_devs;
331 struct snd_pcm *pcm[AZX_MAX_PCMS];
334 unsigned short codec_mask;
341 /* BDL, CORB/RIRB and position buffers */
342 struct snd_dma_buffer bdl;
343 struct snd_dma_buffer rb;
344 struct snd_dma_buffer posbuf;
348 unsigned int initialized :1;
349 unsigned int single_cmd :1;
350 unsigned int polling_mode :1;
354 unsigned int last_cmd; /* last issued command (to sync) */
368 static char *driver_short_names[] __devinitdata = {
369 [AZX_DRIVER_ICH] = "HDA Intel",
370 [AZX_DRIVER_ATI] = "HDA ATI SB",
371 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
372 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
373 [AZX_DRIVER_SIS] = "HDA SIS966",
374 [AZX_DRIVER_ULI] = "HDA ULI M5461",
375 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
379 * macros for easy use
381 #define azx_writel(chip,reg,value) \
382 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
383 #define azx_readl(chip,reg) \
384 readl((chip)->remap_addr + ICH6_REG_##reg)
385 #define azx_writew(chip,reg,value) \
386 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
387 #define azx_readw(chip,reg) \
388 readw((chip)->remap_addr + ICH6_REG_##reg)
389 #define azx_writeb(chip,reg,value) \
390 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
391 #define azx_readb(chip,reg) \
392 readb((chip)->remap_addr + ICH6_REG_##reg)
394 #define azx_sd_writel(dev,reg,value) \
395 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
396 #define azx_sd_readl(dev,reg) \
397 readl((dev)->sd_addr + ICH6_REG_##reg)
398 #define azx_sd_writew(dev,reg,value) \
399 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
400 #define azx_sd_readw(dev,reg) \
401 readw((dev)->sd_addr + ICH6_REG_##reg)
402 #define azx_sd_writeb(dev,reg,value) \
403 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
404 #define azx_sd_readb(dev,reg) \
405 readb((dev)->sd_addr + ICH6_REG_##reg)
407 /* for pcm support */
408 #define get_azx_dev(substream) (substream->runtime->private_data)
410 /* Get the upper 32bit of the given dma_addr_t
411 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
413 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
415 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
418 * Interface for HD codec
422 * CORB / RIRB interface
424 static int azx_alloc_cmd_io(struct azx *chip)
428 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
429 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
430 snd_dma_pci_data(chip->pci),
431 PAGE_SIZE, &chip->rb);
433 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
439 static void azx_init_cmd_io(struct azx *chip)
442 chip->corb.addr = chip->rb.addr;
443 chip->corb.buf = (u32 *)chip->rb.area;
444 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
445 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
447 /* set the corb size to 256 entries (ULI requires explicitly) */
448 azx_writeb(chip, CORBSIZE, 0x02);
449 /* set the corb write pointer to 0 */
450 azx_writew(chip, CORBWP, 0);
451 /* reset the corb hw read pointer */
452 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
453 /* enable corb dma */
454 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
457 chip->rirb.addr = chip->rb.addr + 2048;
458 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
459 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
460 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
462 /* set the rirb size to 256 entries (ULI requires explicitly) */
463 azx_writeb(chip, RIRBSIZE, 0x02);
464 /* reset the rirb hw write pointer */
465 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
466 /* set N=1, get RIRB response interrupt for new entry */
467 azx_writew(chip, RINTCNT, 1);
468 /* enable rirb dma and response irq */
469 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
470 chip->rirb.rp = chip->rirb.cmds = 0;
473 static void azx_free_cmd_io(struct azx *chip)
475 /* disable ringbuffer DMAs */
476 azx_writeb(chip, RIRBCTL, 0);
477 azx_writeb(chip, CORBCTL, 0);
481 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
483 struct azx *chip = codec->bus->private_data;
486 /* add command to corb */
487 wp = azx_readb(chip, CORBWP);
489 wp %= ICH6_MAX_CORB_ENTRIES;
491 spin_lock_irq(&chip->reg_lock);
493 chip->corb.buf[wp] = cpu_to_le32(val);
494 azx_writel(chip, CORBWP, wp);
495 spin_unlock_irq(&chip->reg_lock);
500 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
502 /* retrieve RIRB entry - called from interrupt handler */
503 static void azx_update_rirb(struct azx *chip)
508 wp = azx_readb(chip, RIRBWP);
509 if (wp == chip->rirb.wp)
513 while (chip->rirb.rp != wp) {
515 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
517 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
518 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
519 res = le32_to_cpu(chip->rirb.buf[rp]);
520 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
521 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
522 else if (chip->rirb.cmds) {
524 chip->rirb.res = res;
529 /* receive a response */
530 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
532 struct azx *chip = codec->bus->private_data;
533 unsigned long timeout;
536 timeout = jiffies + msecs_to_jiffies(1000);
538 if (chip->polling_mode) {
539 spin_lock_irq(&chip->reg_lock);
540 azx_update_rirb(chip);
541 spin_unlock_irq(&chip->reg_lock);
543 if (!chip->rirb.cmds)
544 return chip->rirb.res; /* the last value */
546 } while (time_after_eq(timeout, jiffies));
549 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
550 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
551 free_irq(chip->irq, chip);
553 pci_disable_msi(chip->pci);
555 if (azx_acquire_irq(chip, 1) < 0)
560 if (!chip->polling_mode) {
561 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
562 "switching to polling mode: last cmd=0x%08x\n",
564 chip->polling_mode = 1;
568 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
569 "switching to single_cmd mode: last cmd=0x%08x\n",
571 chip->rirb.rp = azx_readb(chip, RIRBWP);
573 /* switch to single_cmd mode */
574 chip->single_cmd = 1;
575 azx_free_cmd_io(chip);
580 * Use the single immediate command instead of CORB/RIRB for simplicity
582 * Note: according to Intel, this is not preferred use. The command was
583 * intended for the BIOS only, and may get confused with unsolicited
584 * responses. So, we shouldn't use it for normal operation from the
586 * I left the codes, however, for debugging/testing purposes.
590 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
592 struct azx *chip = codec->bus->private_data;
596 /* check ICB busy bit */
597 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
598 /* Clear IRV valid bit */
599 azx_writew(chip, IRS, azx_readw(chip, IRS) |
601 azx_writel(chip, IC, val);
602 azx_writew(chip, IRS, azx_readw(chip, IRS) |
608 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
609 azx_readw(chip, IRS), val);
613 /* receive a response */
614 static unsigned int azx_single_get_response(struct hda_codec *codec)
616 struct azx *chip = codec->bus->private_data;
620 /* check IRV busy bit */
621 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
622 return azx_readl(chip, IR);
625 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
626 azx_readw(chip, IRS));
627 return (unsigned int)-1;
631 * The below are the main callbacks from hda_codec.
633 * They are just the skeleton to call sub-callbacks according to the
634 * current setting of chip->single_cmd.
638 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
639 int direct, unsigned int verb,
642 struct azx *chip = codec->bus->private_data;
645 val = (u32)(codec->addr & 0x0f) << 28;
646 val |= (u32)direct << 27;
647 val |= (u32)nid << 20;
650 chip->last_cmd = val;
652 if (chip->single_cmd)
653 return azx_single_send_cmd(codec, val);
655 return azx_corb_send_cmd(codec, val);
659 static unsigned int azx_get_response(struct hda_codec *codec)
661 struct azx *chip = codec->bus->private_data;
662 if (chip->single_cmd)
663 return azx_single_get_response(codec);
665 return azx_rirb_get_response(codec);
669 /* reset codec link */
670 static int azx_reset(struct azx *chip)
674 /* reset controller */
675 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
678 while (azx_readb(chip, GCTL) && --count)
681 /* delay for >= 100us for codec PLL to settle per spec
682 * Rev 0.9 section 5.5.1
686 /* Bring controller out of reset */
687 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
690 while (!azx_readb(chip, GCTL) && --count)
693 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
696 /* check to see if controller is ready */
697 if (!azx_readb(chip, GCTL)) {
698 snd_printd("azx_reset: controller not ready!\n");
702 /* Accept unsolicited responses */
703 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
706 if (!chip->codec_mask) {
707 chip->codec_mask = azx_readw(chip, STATESTS);
708 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
719 /* enable interrupts */
720 static void azx_int_enable(struct azx *chip)
722 /* enable controller CIE and GIE */
723 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
724 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
727 /* disable interrupts */
728 static void azx_int_disable(struct azx *chip)
732 /* disable interrupts in stream descriptor */
733 for (i = 0; i < chip->num_streams; i++) {
734 struct azx_dev *azx_dev = &chip->azx_dev[i];
735 azx_sd_writeb(azx_dev, SD_CTL,
736 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
739 /* disable SIE for all streams */
740 azx_writeb(chip, INTCTL, 0);
742 /* disable controller CIE and GIE */
743 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
744 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
747 /* clear interrupts */
748 static void azx_int_clear(struct azx *chip)
752 /* clear stream status */
753 for (i = 0; i < chip->num_streams; i++) {
754 struct azx_dev *azx_dev = &chip->azx_dev[i];
755 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
759 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
761 /* clear rirb status */
762 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
764 /* clear int status */
765 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
769 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
772 azx_writeb(chip, INTCTL,
773 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
774 /* set DMA start and interrupt mask */
775 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
776 SD_CTL_DMA_START | SD_INT_MASK);
780 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
783 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
784 ~(SD_CTL_DMA_START | SD_INT_MASK));
785 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
787 azx_writeb(chip, INTCTL,
788 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
793 * initialize the chip
795 static void azx_init_chip(struct azx *chip)
799 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
800 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
801 * Ensuring these bits are 0 clears playback static on some HD Audio
804 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, ®);
805 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
807 /* reset controller */
810 /* initialize interrupts */
812 azx_int_enable(chip);
814 /* initialize the codec command I/O */
815 if (!chip->single_cmd)
816 azx_init_cmd_io(chip);
818 /* program the position buffer */
819 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
820 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
822 switch (chip->driver_type) {
824 /* For ATI SB450 azalia HD audio, we need to enable snoop */
825 pci_read_config_byte(chip->pci,
826 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
828 pci_write_config_byte(chip->pci,
829 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
831 ATI_SB450_HDAUDIO_ENABLE_SNOOP);
833 case AZX_DRIVER_NVIDIA:
834 /* For NVIDIA HDA, enable snoop */
835 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, ®);
836 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
837 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
846 static irqreturn_t azx_interrupt(int irq, void *dev_id)
848 struct azx *chip = dev_id;
849 struct azx_dev *azx_dev;
853 spin_lock(&chip->reg_lock);
855 status = azx_readl(chip, INTSTS);
857 spin_unlock(&chip->reg_lock);
861 for (i = 0; i < chip->num_streams; i++) {
862 azx_dev = &chip->azx_dev[i];
863 if (status & azx_dev->sd_int_sta_mask) {
864 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
865 if (azx_dev->substream && azx_dev->running) {
866 azx_dev->period_intr++;
867 spin_unlock(&chip->reg_lock);
868 snd_pcm_period_elapsed(azx_dev->substream);
869 spin_lock(&chip->reg_lock);
875 status = azx_readb(chip, RIRBSTS);
876 if (status & RIRB_INT_MASK) {
877 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
878 azx_update_rirb(chip);
879 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
883 /* clear state status int */
884 if (azx_readb(chip, STATESTS) & 0x04)
885 azx_writeb(chip, STATESTS, 0x04);
887 spin_unlock(&chip->reg_lock);
896 static void azx_setup_periods(struct azx_dev *azx_dev)
898 u32 *bdl = azx_dev->bdl;
899 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
902 /* reset BDL address */
903 azx_sd_writel(azx_dev, SD_BDLPL, 0);
904 azx_sd_writel(azx_dev, SD_BDLPU, 0);
906 /* program the initial BDL entries */
907 for (idx = 0; idx < azx_dev->frags; idx++) {
908 unsigned int off = idx << 2; /* 4 dword step */
909 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
910 /* program the address field of the BDL entry */
911 bdl[off] = cpu_to_le32((u32)addr);
912 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
914 /* program the size field of the BDL entry */
915 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
917 /* program the IOC to enable interrupt when buffer completes */
918 bdl[off+3] = cpu_to_le32(0x01);
923 * set up the SD for streaming
925 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
930 /* make sure the run bit is zero for SD */
931 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
934 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
935 SD_CTL_STREAM_RESET);
938 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
941 val &= ~SD_CTL_STREAM_RESET;
942 azx_sd_writeb(azx_dev, SD_CTL, val);
946 /* waiting for hardware to report that the stream is out of reset */
947 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
951 /* program the stream_tag */
952 azx_sd_writel(azx_dev, SD_CTL,
953 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
954 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
956 /* program the length of samples in cyclic buffer */
957 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
959 /* program the stream format */
960 /* this value needs to be the same as the one programmed */
961 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
963 /* program the stream LVI (last valid index) of the BDL */
964 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
966 /* program the BDL address */
967 /* lower BDL address */
968 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
969 /* upper BDL address */
970 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
972 /* enable the position buffer */
973 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
974 azx_writel(chip, DPLBASE,
975 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
977 /* set the interrupt enable bits in the descriptor control register */
978 azx_sd_writel(azx_dev, SD_CTL,
979 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
986 * Codec initialization
989 static unsigned int azx_max_codecs[] __devinitdata = {
990 [AZX_DRIVER_ICH] = 3,
991 [AZX_DRIVER_ATI] = 4,
992 [AZX_DRIVER_ATIHDMI] = 4,
993 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
994 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
995 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
996 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
999 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1001 struct hda_bus_template bus_temp;
1002 int c, codecs, audio_codecs, err;
1004 memset(&bus_temp, 0, sizeof(bus_temp));
1005 bus_temp.private_data = chip;
1006 bus_temp.modelname = model;
1007 bus_temp.pci = chip->pci;
1008 bus_temp.ops.command = azx_send_cmd;
1009 bus_temp.ops.get_response = azx_get_response;
1011 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1015 codecs = audio_codecs = 0;
1016 for (c = 0; c < AZX_MAX_CODECS; c++) {
1017 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1018 struct hda_codec *codec;
1019 err = snd_hda_codec_new(chip->bus, c, &codec);
1027 if (!audio_codecs) {
1028 /* probe additional slots if no codec is found */
1029 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1030 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1031 err = snd_hda_codec_new(chip->bus, c, NULL);
1039 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1051 /* assign a stream for the PCM */
1052 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1055 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1056 dev = chip->playback_index_offset;
1057 nums = chip->playback_streams;
1059 dev = chip->capture_index_offset;
1060 nums = chip->capture_streams;
1062 for (i = 0; i < nums; i++, dev++)
1063 if (!chip->azx_dev[dev].opened) {
1064 chip->azx_dev[dev].opened = 1;
1065 return &chip->azx_dev[dev];
1070 /* release the assigned stream */
1071 static inline void azx_release_device(struct azx_dev *azx_dev)
1073 azx_dev->opened = 0;
1076 static struct snd_pcm_hardware azx_pcm_hw = {
1077 .info = (SNDRV_PCM_INFO_MMAP |
1078 SNDRV_PCM_INFO_INTERLEAVED |
1079 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1080 SNDRV_PCM_INFO_MMAP_VALID |
1081 /* No full-resume yet implemented */
1082 /* SNDRV_PCM_INFO_RESUME |*/
1083 SNDRV_PCM_INFO_PAUSE),
1084 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1085 .rates = SNDRV_PCM_RATE_48000,
1090 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1091 .period_bytes_min = 128,
1092 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1094 .periods_max = AZX_MAX_FRAG,
1100 struct hda_codec *codec;
1101 struct hda_pcm_stream *hinfo[2];
1104 static int azx_pcm_open(struct snd_pcm_substream *substream)
1106 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1107 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1108 struct azx *chip = apcm->chip;
1109 struct azx_dev *azx_dev;
1110 struct snd_pcm_runtime *runtime = substream->runtime;
1111 unsigned long flags;
1114 mutex_lock(&chip->open_mutex);
1115 azx_dev = azx_assign_device(chip, substream->stream);
1116 if (azx_dev == NULL) {
1117 mutex_unlock(&chip->open_mutex);
1120 runtime->hw = azx_pcm_hw;
1121 runtime->hw.channels_min = hinfo->channels_min;
1122 runtime->hw.channels_max = hinfo->channels_max;
1123 runtime->hw.formats = hinfo->formats;
1124 runtime->hw.rates = hinfo->rates;
1125 snd_pcm_limit_hw_rates(runtime);
1126 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1127 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1129 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1131 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1133 azx_release_device(azx_dev);
1134 mutex_unlock(&chip->open_mutex);
1137 spin_lock_irqsave(&chip->reg_lock, flags);
1138 azx_dev->substream = substream;
1139 azx_dev->running = 0;
1140 spin_unlock_irqrestore(&chip->reg_lock, flags);
1142 runtime->private_data = azx_dev;
1143 mutex_unlock(&chip->open_mutex);
1147 static int azx_pcm_close(struct snd_pcm_substream *substream)
1149 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1150 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1151 struct azx *chip = apcm->chip;
1152 struct azx_dev *azx_dev = get_azx_dev(substream);
1153 unsigned long flags;
1155 mutex_lock(&chip->open_mutex);
1156 spin_lock_irqsave(&chip->reg_lock, flags);
1157 azx_dev->substream = NULL;
1158 azx_dev->running = 0;
1159 spin_unlock_irqrestore(&chip->reg_lock, flags);
1160 azx_release_device(azx_dev);
1161 hinfo->ops.close(hinfo, apcm->codec, substream);
1162 mutex_unlock(&chip->open_mutex);
1166 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1167 struct snd_pcm_hw_params *hw_params)
1169 return snd_pcm_lib_malloc_pages(substream,
1170 params_buffer_bytes(hw_params));
1173 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1175 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1176 struct azx_dev *azx_dev = get_azx_dev(substream);
1177 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1179 /* reset BDL address */
1180 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1181 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1182 azx_sd_writel(azx_dev, SD_CTL, 0);
1184 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1186 return snd_pcm_lib_free_pages(substream);
1189 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1191 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1192 struct azx *chip = apcm->chip;
1193 struct azx_dev *azx_dev = get_azx_dev(substream);
1194 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1195 struct snd_pcm_runtime *runtime = substream->runtime;
1197 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1198 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1199 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1200 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1204 if (!azx_dev->format_val) {
1205 snd_printk(KERN_ERR SFX
1206 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1207 runtime->rate, runtime->channels, runtime->format);
1211 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1213 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1214 azx_setup_periods(azx_dev);
1215 azx_setup_controller(chip, azx_dev);
1216 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1217 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1219 azx_dev->fifo_size = 0;
1221 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1222 azx_dev->format_val, substream);
1225 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1227 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1228 struct azx_dev *azx_dev = get_azx_dev(substream);
1229 struct azx *chip = apcm->chip;
1232 spin_lock(&chip->reg_lock);
1234 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1235 case SNDRV_PCM_TRIGGER_RESUME:
1236 case SNDRV_PCM_TRIGGER_START:
1237 azx_stream_start(chip, azx_dev);
1238 azx_dev->running = 1;
1240 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1241 case SNDRV_PCM_TRIGGER_SUSPEND:
1242 case SNDRV_PCM_TRIGGER_STOP:
1243 azx_stream_stop(chip, azx_dev);
1244 azx_dev->running = 0;
1249 spin_unlock(&chip->reg_lock);
1250 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1251 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1252 cmd == SNDRV_PCM_TRIGGER_STOP) {
1254 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1261 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1263 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1264 struct azx *chip = apcm->chip;
1265 struct azx_dev *azx_dev = get_azx_dev(substream);
1268 if (chip->position_fix == POS_FIX_POSBUF ||
1269 chip->position_fix == POS_FIX_AUTO) {
1270 /* use the position buffer */
1271 pos = le32_to_cpu(*azx_dev->posbuf);
1272 if (chip->position_fix == POS_FIX_AUTO &&
1273 azx_dev->period_intr == 1 && !pos) {
1275 "hda-intel: Invalid position buffer, "
1276 "using LPIB read method instead.\n");
1277 chip->position_fix = POS_FIX_NONE;
1283 pos = azx_sd_readl(azx_dev, SD_LPIB);
1284 if (chip->position_fix == POS_FIX_FIFO)
1285 pos += azx_dev->fifo_size;
1287 if (pos >= azx_dev->bufsize)
1289 return bytes_to_frames(substream->runtime, pos);
1292 static struct snd_pcm_ops azx_pcm_ops = {
1293 .open = azx_pcm_open,
1294 .close = azx_pcm_close,
1295 .ioctl = snd_pcm_lib_ioctl,
1296 .hw_params = azx_pcm_hw_params,
1297 .hw_free = azx_pcm_hw_free,
1298 .prepare = azx_pcm_prepare,
1299 .trigger = azx_pcm_trigger,
1300 .pointer = azx_pcm_pointer,
1303 static void azx_pcm_free(struct snd_pcm *pcm)
1305 kfree(pcm->private_data);
1308 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1309 struct hda_pcm *cpcm, int pcm_dev)
1312 struct snd_pcm *pcm;
1313 struct azx_pcm *apcm;
1315 /* if no substreams are defined for both playback and capture,
1316 * it's just a placeholder. ignore it.
1318 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1321 snd_assert(cpcm->name, return -EINVAL);
1323 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1324 cpcm->stream[0].substreams,
1325 cpcm->stream[1].substreams,
1329 strcpy(pcm->name, cpcm->name);
1330 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1334 apcm->codec = codec;
1335 apcm->hinfo[0] = &cpcm->stream[0];
1336 apcm->hinfo[1] = &cpcm->stream[1];
1337 pcm->private_data = apcm;
1338 pcm->private_free = azx_pcm_free;
1339 if (cpcm->stream[0].substreams)
1340 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1341 if (cpcm->stream[1].substreams)
1342 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1343 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1344 snd_dma_pci_data(chip->pci),
1345 1024 * 64, 1024 * 1024);
1346 chip->pcm[pcm_dev] = pcm;
1347 if (chip->pcm_devs < pcm_dev + 1)
1348 chip->pcm_devs = pcm_dev + 1;
1353 static int __devinit azx_pcm_create(struct azx *chip)
1355 struct list_head *p;
1356 struct hda_codec *codec;
1360 err = snd_hda_build_pcms(chip->bus);
1364 /* create audio PCMs */
1366 list_for_each(p, &chip->bus->codec_list) {
1367 codec = list_entry(p, struct hda_codec, list);
1368 for (c = 0; c < codec->num_pcms; c++) {
1369 if (codec->pcm_info[c].is_modem)
1370 continue; /* create later */
1371 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1372 snd_printk(KERN_ERR SFX
1373 "Too many audio PCMs\n");
1376 err = create_codec_pcm(chip, codec,
1377 &codec->pcm_info[c], pcm_dev);
1384 /* create modem PCMs */
1385 pcm_dev = AZX_MAX_AUDIO_PCMS;
1386 list_for_each(p, &chip->bus->codec_list) {
1387 codec = list_entry(p, struct hda_codec, list);
1388 for (c = 0; c < codec->num_pcms; c++) {
1389 if (!codec->pcm_info[c].is_modem)
1390 continue; /* already created */
1391 if (pcm_dev >= AZX_MAX_PCMS) {
1392 snd_printk(KERN_ERR SFX
1393 "Too many modem PCMs\n");
1396 err = create_codec_pcm(chip, codec,
1397 &codec->pcm_info[c], pcm_dev);
1400 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1408 * mixer creation - all stuff is implemented in hda module
1410 static int __devinit azx_mixer_create(struct azx *chip)
1412 return snd_hda_build_controls(chip->bus);
1417 * initialize SD streams
1419 static int __devinit azx_init_stream(struct azx *chip)
1423 /* initialize each stream (aka device)
1424 * assign the starting bdl address to each stream (device)
1427 for (i = 0; i < chip->num_streams; i++) {
1428 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1429 struct azx_dev *azx_dev = &chip->azx_dev[i];
1430 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1431 azx_dev->bdl_addr = chip->bdl.addr + off;
1432 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1433 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1434 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1435 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1436 azx_dev->sd_int_sta_mask = 1 << i;
1437 /* stream tag: must be non-zero and unique */
1439 azx_dev->stream_tag = i + 1;
1445 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1447 if (request_irq(chip->pci->irq, azx_interrupt,
1448 chip->msi ? 0 : IRQF_SHARED,
1449 "HDA Intel", chip)) {
1450 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1451 "disabling device\n", chip->pci->irq);
1453 snd_card_disconnect(chip->card);
1456 chip->irq = chip->pci->irq;
1457 pci_intx(chip->pci, !chip->msi);
1466 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1468 struct snd_card *card = pci_get_drvdata(pci);
1469 struct azx *chip = card->private_data;
1472 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1473 for (i = 0; i < chip->pcm_devs; i++)
1474 snd_pcm_suspend_all(chip->pcm[i]);
1475 snd_hda_suspend(chip->bus, state);
1476 azx_free_cmd_io(chip);
1477 if (chip->irq >= 0) {
1478 synchronize_irq(chip->irq);
1479 free_irq(chip->irq, chip);
1483 pci_disable_msi(chip->pci);
1484 pci_disable_device(pci);
1485 pci_save_state(pci);
1486 pci_set_power_state(pci, pci_choose_state(pci, state));
1490 static int azx_resume(struct pci_dev *pci)
1492 struct snd_card *card = pci_get_drvdata(pci);
1493 struct azx *chip = card->private_data;
1495 pci_set_power_state(pci, PCI_D0);
1496 pci_restore_state(pci);
1497 if (pci_enable_device(pci) < 0) {
1498 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1499 "disabling device\n");
1500 snd_card_disconnect(card);
1503 pci_set_master(pci);
1505 if (pci_enable_msi(pci) < 0)
1507 if (azx_acquire_irq(chip, 1) < 0)
1509 azx_init_chip(chip);
1510 snd_hda_resume(chip->bus);
1511 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1514 #endif /* CONFIG_PM */
1520 static int azx_free(struct azx *chip)
1522 if (chip->initialized) {
1525 for (i = 0; i < chip->num_streams; i++)
1526 azx_stream_stop(chip, &chip->azx_dev[i]);
1528 /* disable interrupts */
1529 azx_int_disable(chip);
1530 azx_int_clear(chip);
1532 /* disable CORB/RIRB */
1533 azx_free_cmd_io(chip);
1535 /* disable position buffer */
1536 azx_writel(chip, DPLBASE, 0);
1537 azx_writel(chip, DPUBASE, 0);
1540 if (chip->irq >= 0) {
1541 synchronize_irq(chip->irq);
1542 free_irq(chip->irq, (void*)chip);
1545 pci_disable_msi(chip->pci);
1546 if (chip->remap_addr)
1547 iounmap(chip->remap_addr);
1550 snd_dma_free_pages(&chip->bdl);
1552 snd_dma_free_pages(&chip->rb);
1553 if (chip->posbuf.area)
1554 snd_dma_free_pages(&chip->posbuf);
1555 pci_release_regions(chip->pci);
1556 pci_disable_device(chip->pci);
1557 kfree(chip->azx_dev);
1563 static int azx_dev_free(struct snd_device *device)
1565 return azx_free(device->device_data);
1569 * white/black-listing for position_fix
1571 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1572 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1576 static int __devinit check_position_fix(struct azx *chip, int fix)
1578 const struct snd_pci_quirk *q;
1580 if (fix == POS_FIX_AUTO) {
1581 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1583 snd_printdd(KERN_INFO
1584 "hda_intel: position_fix set to %d "
1585 "for device %04x:%04x\n",
1586 q->value, q->subvendor, q->subdevice);
1596 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1602 static struct snd_device_ops ops = {
1603 .dev_free = azx_dev_free,
1608 err = pci_enable_device(pci);
1612 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1614 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1615 pci_disable_device(pci);
1619 spin_lock_init(&chip->reg_lock);
1620 mutex_init(&chip->open_mutex);
1624 chip->driver_type = driver_type;
1625 chip->msi = enable_msi;
1627 chip->position_fix = check_position_fix(chip, position_fix);
1629 chip->single_cmd = single_cmd;
1631 #if BITS_PER_LONG != 64
1632 /* Fix up base address on ULI M5461 */
1633 if (chip->driver_type == AZX_DRIVER_ULI) {
1635 pci_read_config_word(pci, 0x40, &tmp3);
1636 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1637 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1641 err = pci_request_regions(pci, "ICH HD audio");
1644 pci_disable_device(pci);
1648 chip->addr = pci_resource_start(pci, 0);
1649 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1650 if (chip->remap_addr == NULL) {
1651 snd_printk(KERN_ERR SFX "ioremap error\n");
1657 if (pci_enable_msi(pci) < 0)
1660 if (azx_acquire_irq(chip, 0) < 0) {
1665 pci_set_master(pci);
1666 synchronize_irq(chip->irq);
1668 switch (chip->driver_type) {
1669 case AZX_DRIVER_ULI:
1670 chip->playback_streams = ULI_NUM_PLAYBACK;
1671 chip->capture_streams = ULI_NUM_CAPTURE;
1672 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1673 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1675 case AZX_DRIVER_ATIHDMI:
1676 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1677 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1678 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1679 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1682 chip->playback_streams = ICH6_NUM_PLAYBACK;
1683 chip->capture_streams = ICH6_NUM_CAPTURE;
1684 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1685 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1688 chip->num_streams = chip->playback_streams + chip->capture_streams;
1689 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1691 if (!chip->azx_dev) {
1692 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1696 /* allocate memory for the BDL for each stream */
1697 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1698 snd_dma_pci_data(chip->pci),
1699 BDL_SIZE, &chip->bdl);
1701 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1704 /* allocate memory for the position buffer */
1705 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1706 snd_dma_pci_data(chip->pci),
1707 chip->num_streams * 8, &chip->posbuf);
1709 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1712 /* allocate CORB/RIRB */
1713 if (!chip->single_cmd) {
1714 err = azx_alloc_cmd_io(chip);
1719 /* initialize streams */
1720 azx_init_stream(chip);
1722 /* initialize chip */
1723 azx_init_chip(chip);
1725 chip->initialized = 1;
1727 /* codec detection */
1728 if (!chip->codec_mask) {
1729 snd_printk(KERN_ERR SFX "no codecs found!\n");
1734 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1736 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1740 strcpy(card->driver, "HDA-Intel");
1741 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1742 sprintf(card->longname, "%s at 0x%lx irq %i",
1743 card->shortname, chip->addr, chip->irq);
1753 static int __devinit azx_probe(struct pci_dev *pci,
1754 const struct pci_device_id *pci_id)
1756 struct snd_card *card;
1760 card = snd_card_new(index, id, THIS_MODULE, 0);
1762 snd_printk(KERN_ERR SFX "Error creating card!\n");
1766 err = azx_create(card, pci, pci_id->driver_data, &chip);
1768 snd_card_free(card);
1771 card->private_data = chip;
1773 /* create codec instances */
1774 err = azx_codec_create(chip, model);
1776 snd_card_free(card);
1780 /* create PCM streams */
1781 err = azx_pcm_create(chip);
1783 snd_card_free(card);
1787 /* create mixer controls */
1788 err = azx_mixer_create(chip);
1790 snd_card_free(card);
1794 snd_card_set_dev(card, &pci->dev);
1796 err = snd_card_register(card);
1798 snd_card_free(card);
1802 pci_set_drvdata(pci, card);
1807 static void __devexit azx_remove(struct pci_dev *pci)
1809 snd_card_free(pci_get_drvdata(pci));
1810 pci_set_drvdata(pci, NULL);
1814 static struct pci_device_id azx_ids[] = {
1815 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1816 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1817 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1818 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1819 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1820 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1821 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1822 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1823 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1824 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1825 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1826 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1827 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1828 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1829 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1830 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1831 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1832 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1833 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1834 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1835 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1836 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1837 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1838 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1839 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1840 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1841 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1842 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1843 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1846 MODULE_DEVICE_TABLE(pci, azx_ids);
1848 /* pci_driver definition */
1849 static struct pci_driver driver = {
1850 .name = "HDA Intel",
1851 .id_table = azx_ids,
1853 .remove = __devexit_p(azx_remove),
1855 .suspend = azx_suspend,
1856 .resume = azx_resume,
1860 static int __init alsa_card_azx_init(void)
1862 return pci_register_driver(&driver);
1865 static void __exit alsa_card_azx_exit(void)
1867 pci_unregister_driver(&driver);
1870 module_init(alsa_card_azx_init)
1871 module_exit(alsa_card_azx_exit)