err.no Git - linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along with
  21  *  this program; if not, write to the Free Software Foundation, Inc., 59
  22  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23  *
  24  *  CONTACTS:
  25  *
  26  *  Matt Jared          matt.jared@intel.com
  27  *  Andy Kopp           andy.kopp@intel.com
  28  *  Dan Kogan           dan.d.kogan@intel.com
  29  *
  30  *  CHANGES:
  31  *
  32  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  33  *
  34  */
  35
  36 #include <sound/driver.h>
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/init.h>
  43 #include <linux/slab.h>
  44 #include <linux/pci.h>
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include "hda_codec.h"
  48
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  53 static char *model[SNDRV_CARDS];
  54 static int position_fix[SNDRV_CARDS];
  55
  56 module_param_array(index, int, NULL, 0444);
  57 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  58 module_param_array(id, charp, NULL, 0444);
  59 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  60 module_param_array(enable, bool, NULL, 0444);
  61 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  62 module_param_array(model, charp, NULL, 0444);
  63 MODULE_PARM_DESC(model, "Use the given board model.");
  64 module_param_array(position_fix, bool, NULL, 0444);
  65 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF).");
  66
  67 MODULE_LICENSE("GPL");
  68 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  69                          "{Intel, ICH6M},"
  70                          "{Intel, ICH7},"
  71                          "{Intel, ESB2}}");
  72 MODULE_DESCRIPTION("Intel HDA driver");
  73
  74 #define SFX     "hda-intel: "
  75
  76 /*
  77  * registers
  78  */
  79 #define ICH6_REG_GCAP                   0x00
  80 #define ICH6_REG_VMIN                   0x02
  81 #define ICH6_REG_VMAJ                   0x03
  82 #define ICH6_REG_OUTPAY                 0x04
  83 #define ICH6_REG_INPAY                  0x06
  84 #define ICH6_REG_GCTL                   0x08
  85 #define ICH6_REG_WAKEEN                 0x0c
  86 #define ICH6_REG_STATESTS               0x0e
  87 #define ICH6_REG_GSTS                   0x10
  88 #define ICH6_REG_INTCTL                 0x20
  89 #define ICH6_REG_INTSTS                 0x24
  90 #define ICH6_REG_WALCLK                 0x30
  91 #define ICH6_REG_SYNC                   0x34
  92 #define ICH6_REG_CORBLBASE              0x40
  93 #define ICH6_REG_CORBUBASE              0x44
  94 #define ICH6_REG_CORBWP                 0x48
  95 #define ICH6_REG_CORBRP                 0x4A
  96 #define ICH6_REG_CORBCTL                0x4c
  97 #define ICH6_REG_CORBSTS                0x4d
  98 #define ICH6_REG_CORBSIZE               0x4e
  99
 100 #define ICH6_REG_RIRBLBASE              0x50
 101 #define ICH6_REG_RIRBUBASE              0x54
 102 #define ICH6_REG_RIRBWP                 0x58
 103 #define ICH6_REG_RINTCNT                0x5a
 104 #define ICH6_REG_RIRBCTL                0x5c
 105 #define ICH6_REG_RIRBSTS                0x5d
 106 #define ICH6_REG_RIRBSIZE               0x5e
 107
 108 #define ICH6_REG_IC                     0x60
 109 #define ICH6_REG_IR                     0x64
 110 #define ICH6_REG_IRS                    0x68
 111 #define   ICH6_IRS_VALID        (1<<1)
 112 #define   ICH6_IRS_BUSY         (1<<0)
 113
 114 #define ICH6_REG_DPLBASE                0x70
 115 #define ICH6_REG_DPUBASE                0x74
 116 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 117
 118 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 119 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 120
 121 /* stream register offsets from stream base */
 122 #define ICH6_REG_SD_CTL                 0x00
 123 #define ICH6_REG_SD_STS                 0x03
 124 #define ICH6_REG_SD_LPIB                0x04
 125 #define ICH6_REG_SD_CBL                 0x08
 126 #define ICH6_REG_SD_LVI                 0x0c
 127 #define ICH6_REG_SD_FIFOW               0x0e
 128 #define ICH6_REG_SD_FIFOSIZE            0x10
 129 #define ICH6_REG_SD_FORMAT              0x12
 130 #define ICH6_REG_SD_BDLPL               0x18
 131 #define ICH6_REG_SD_BDLPU               0x1c
 132
 133 /* PCI space */
 134 #define ICH6_PCIREG_TCSEL       0x44
 135
 136 /*
 137  * other constants
 138  */
 139
 140 /* max number of SDs */
 141 #define MAX_ICH6_DEV            8
 142 /* max number of fragments - we may use more if allocating more pages for BDL */
 143 #define AZX_MAX_FRAG            (PAGE_SIZE / (MAX_ICH6_DEV * 16))
 144 /* max buffer size - no h/w limit, you can increase as you like */
 145 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 146 /* max number of PCM devics per card */
 147 #define AZX_MAX_PCMS            8
 148
 149 /* RIRB int mask: overrun[2], response[0] */
 150 #define RIRB_INT_RESPONSE       0x01
 151 #define RIRB_INT_OVERRUN        0x04
 152 #define RIRB_INT_MASK           0x05
 153
 154 /* STATESTS int mask: SD2,SD1,SD0 */
 155 #define STATESTS_INT_MASK       0x07
 156 #define AZX_MAX_CODECS          3
 157
 158 /* SD_CTL bits */
 159 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 160 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 161 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 162 #define SD_CTL_STREAM_TAG_SHIFT 20
 163
 164 /* SD_CTL and SD_STS */
 165 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 166 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 167 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 168 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
 169
 170 /* SD_STS */
 171 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 172
 173 /* INTCTL and INTSTS */
 174 #define ICH6_INT_ALL_STREAM     0xff            /* all stream interrupts */
 175 #define ICH6_INT_CTRL_EN        0x40000000      /* controller interrupt enable bit */
 176 #define ICH6_INT_GLOBAL_EN      0x80000000      /* global interrupt enable bit */
 177
 178 /* GCTL reset bit */
 179 #define ICH6_GCTL_RESET         (1<<0)
 180
 181 /* CORB/RIRB control, read/write pointer */
 182 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 183 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 184 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 185 /* below are so far hardcoded - should read registers in future */
 186 #define ICH6_MAX_CORB_ENTRIES   256
 187 #define ICH6_MAX_RIRB_ENTRIES   256
 188
 189 /* position fix mode */
 190 enum {
 191         POS_FIX_FIFO,
 192         POS_FIX_NONE,
 193         POS_FIX_POSBUF
 194 };
 195
 196 /*
 197  * Use CORB/RIRB for communication from/to codecs.
 198  * This is the way recommended by Intel (see below).
 199  */
 200 #define USE_CORB_RIRB
 201
 202 /*
 203  */
 204
 205 typedef struct snd_azx azx_t;
 206 typedef struct snd_azx_rb azx_rb_t;
 207 typedef struct snd_azx_dev azx_dev_t;
 208
 209 struct snd_azx_dev {
 210         u32 *bdl;                       /* virtual address of the BDL */
 211         dma_addr_t bdl_addr;            /* physical address of the BDL */
 212         volatile u32 *posbuf;                   /* position buffer pointer */
 213
 214         unsigned int bufsize;           /* size of the play buffer in bytes */
 215         unsigned int fragsize;          /* size of each period in bytes */
 216         unsigned int frags;             /* number for period in the play buffer */
 217         unsigned int fifo_size;         /* FIFO size */
 218
 219         void __iomem *sd_addr;          /* stream descriptor pointer */
 220
 221         u32 sd_int_sta_mask;            /* stream int status mask */
 222
 223         /* pcm support */
 224         snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
 225         unsigned int format_val;        /* format value to be set in the controller and the codec */
 226         unsigned char stream_tag;       /* assigned stream */
 227         unsigned char index;            /* stream index */
 228
 229         unsigned int opened: 1;
 230         unsigned int running: 1;
 231 };
 232
 233 /* CORB/RIRB */
 234 struct snd_azx_rb {
 235         u32 *buf;               /* CORB/RIRB buffer
 236                                  * Each CORB entry is 4byte, RIRB is 8byte
 237                                  */
 238         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 239         /* for RIRB */
 240         unsigned short rp, wp;  /* read/write pointers */
 241         int cmds;               /* number of pending requests */
 242         u32 res;                /* last read value */
 243 };
 244
 245 struct snd_azx {
 246         snd_card_t *card;
 247         struct pci_dev *pci;
 248
 249         /* pci resources */
 250         unsigned long addr;
 251         void __iomem *remap_addr;
 252         int irq;
 253
 254         /* locks */
 255         spinlock_t reg_lock;
 256         struct semaphore open_mutex;
 257
 258         /* streams */
 259         azx_dev_t azx_dev[MAX_ICH6_DEV];
 260
 261         /* PCM */
 262         unsigned int pcm_devs;
 263         snd_pcm_t *pcm[AZX_MAX_PCMS];
 264
 265         /* HD codec */
 266         unsigned short codec_mask;
 267         struct hda_bus *bus;
 268
 269         /* CORB/RIRB */
 270         azx_rb_t corb;
 271         azx_rb_t rirb;
 272
 273         /* BDL, CORB/RIRB and position buffers */
 274         struct snd_dma_buffer bdl;
 275         struct snd_dma_buffer rb;
 276         struct snd_dma_buffer posbuf;
 277
 278         /* flags */
 279         int position_fix;
 280 };
 281
 282 /*
 283  * macros for easy use
 284  */
 285 #define azx_writel(chip,reg,value) \
 286         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 287 #define azx_readl(chip,reg) \
 288         readl((chip)->remap_addr + ICH6_REG_##reg)
 289 #define azx_writew(chip,reg,value) \
 290         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 291 #define azx_readw(chip,reg) \
 292         readw((chip)->remap_addr + ICH6_REG_##reg)
 293 #define azx_writeb(chip,reg,value) \
 294         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 295 #define azx_readb(chip,reg) \
 296         readb((chip)->remap_addr + ICH6_REG_##reg)
 297
 298 #define azx_sd_writel(dev,reg,value) \
 299         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 300 #define azx_sd_readl(dev,reg) \
 301         readl((dev)->sd_addr + ICH6_REG_##reg)
 302 #define azx_sd_writew(dev,reg,value) \
 303         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 304 #define azx_sd_readw(dev,reg) \
 305         readw((dev)->sd_addr + ICH6_REG_##reg)
 306 #define azx_sd_writeb(dev,reg,value) \
 307         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 308 #define azx_sd_readb(dev,reg) \
 309         readb((dev)->sd_addr + ICH6_REG_##reg)
 310
 311 /* for pcm support */
 312 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
 313
 314 /* Get the upper 32bit of the given dma_addr_t
 315  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 316  */
 317 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 318
 319
 320 /*
 321  * Interface for HD codec
 322  */
 323
 324 #ifdef USE_CORB_RIRB
 325 /*
 326  * CORB / RIRB interface
 327  */
 328 static int azx_alloc_cmd_io(azx_t *chip)
 329 {
 330         int err;
 331
 332         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 333         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
 334                                   PAGE_SIZE, &chip->rb);
 335         if (err < 0) {
 336                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 337                 return err;
 338         }
 339         return 0;
 340 }
 341
 342 static void azx_init_cmd_io(azx_t *chip)
 343 {
 344         /* CORB set up */
 345         chip->corb.addr = chip->rb.addr;
 346         chip->corb.buf = (u32 *)chip->rb.area;
 347         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 348         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 349
 350         /* set the corb write pointer to 0 */
 351         azx_writew(chip, CORBWP, 0);
 352         /* reset the corb hw read pointer */
 353         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 354         /* enable corb dma */
 355         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 356
 357         /* RIRB set up */
 358         chip->rirb.addr = chip->rb.addr + 2048;
 359         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 360         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 361         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 362
 363         /* reset the rirb hw write pointer */
 364         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 365         /* set N=1, get RIRB response interrupt for new entry */
 366         azx_writew(chip, RINTCNT, 1);
 367         /* enable rirb dma and response irq */
 368 #ifdef USE_CORB_RIRB
 369         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 370 #else
 371         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
 372 #endif
 373         chip->rirb.rp = chip->rirb.cmds = 0;
 374 }
 375
 376 static void azx_free_cmd_io(azx_t *chip)
 377 {
 378         /* disable ringbuffer DMAs */
 379         azx_writeb(chip, RIRBCTL, 0);
 380         azx_writeb(chip, CORBCTL, 0);
 381 }
 382
 383 /* send a command */
 384 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 385                         unsigned int verb, unsigned int para)
 386 {
 387         azx_t *chip = codec->bus->private_data;
 388         unsigned int wp;
 389         u32 val;
 390
 391         val = (u32)(codec->addr & 0x0f) << 28;
 392         val |= (u32)direct << 27;
 393         val |= (u32)nid << 20;
 394         val |= verb << 8;
 395         val |= para;
 396
 397         /* add command to corb */
 398         wp = azx_readb(chip, CORBWP);
 399         wp++;
 400         wp %= ICH6_MAX_CORB_ENTRIES;
 401
 402         spin_lock_irq(&chip->reg_lock);
 403         chip->rirb.cmds++;
 404         chip->corb.buf[wp] = cpu_to_le32(val);
 405         azx_writel(chip, CORBWP, wp);
 406         spin_unlock_irq(&chip->reg_lock);
 407
 408         return 0;
 409 }
 410
 411 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 412
 413 /* retrieve RIRB entry - called from interrupt handler */
 414 static void azx_update_rirb(azx_t *chip)
 415 {
 416         unsigned int rp, wp;
 417         u32 res, res_ex;
 418
 419         wp = azx_readb(chip, RIRBWP);
 420         if (wp == chip->rirb.wp)
 421                 return;
 422         chip->rirb.wp = wp;
 423
 424         while (chip->rirb.rp != wp) {
 425                 chip->rirb.rp++;
 426                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 427
 428                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 429                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 430                 res = le32_to_cpu(chip->rirb.buf[rp]);
 431                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 432                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 433                 else if (chip->rirb.cmds) {
 434                         chip->rirb.cmds--;
 435                         chip->rirb.res = res;
 436                 }
 437         }
 438 }
 439
 440 /* receive a response */
 441 static unsigned int azx_get_response(struct hda_codec *codec)
 442 {
 443         azx_t *chip = codec->bus->private_data;
 444         int timeout = 50;
 445
 446         while (chip->rirb.cmds) {
 447                 if (! --timeout) {
 448                         snd_printk(KERN_ERR "azx_get_response timeout\n");
 449                         chip->rirb.rp = azx_readb(chip, RIRBWP);
 450                         chip->rirb.cmds = 0;
 451                         return -1;
 452                 }
 453                 msleep(1);
 454         }
 455         return chip->rirb.res; /* the last value */
 456 }
 457
 458 #else
 459 /*
 460  * Use the single immediate command instead of CORB/RIRB for simplicity
 461  *
 462  * Note: according to Intel, this is not preferred use.  The command was
 463  *       intended for the BIOS only, and may get confused with unsolicited
 464  *       responses.  So, we shouldn't use it for normal operation from the
 465  *       driver.
 466  *       I left the codes, however, for debugging/testing purposes.
 467  */
 468
 469 #define azx_alloc_cmd_io(chip)  0
 470 #define azx_init_cmd_io(chip)
 471 #define azx_free_cmd_io(chip)
 472
 473 /* send a command */
 474 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 475                         unsigned int verb, unsigned int para)
 476 {
 477         azx_t *chip = codec->bus->private_data;
 478         u32 val;
 479         int timeout = 50;
 480
 481         val = (u32)(codec->addr & 0x0f) << 28;
 482         val |= (u32)direct << 27;
 483         val |= (u32)nid << 20;
 484         val |= verb << 8;
 485         val |= para;
 486
 487         while (timeout--) {
 488                 /* check ICB busy bit */
 489                 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
 490                         /* Clear IRV valid bit */
 491                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
 492                         azx_writel(chip, IC, val);
 493                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
 494                         return 0;
 495                 }
 496                 udelay(1);
 497         }
 498         snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
 499         return -EIO;
 500 }
 501
 502 /* receive a response */
 503 static unsigned int azx_get_response(struct hda_codec *codec)
 504 {
 505         azx_t *chip = codec->bus->private_data;
 506         int timeout = 50;
 507
 508         while (timeout--) {
 509                 /* check IRV busy bit */
 510                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 511                         return azx_readl(chip, IR);
 512                 udelay(1);
 513         }
 514         snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
 515         return (unsigned int)-1;
 516 }
 517
 518 #define azx_update_rirb(chip)
 519
 520 #endif /* USE_CORB_RIRB */
 521
 522 /* reset codec link */
 523 static int azx_reset(azx_t *chip)
 524 {
 525         int count;
 526
 527         /* reset controller */
 528         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 529
 530         count = 50;
 531         while (azx_readb(chip, GCTL) && --count)
 532                 msleep(1);
 533
 534         /* delay for >= 100us for codec PLL to settle per spec
 535          * Rev 0.9 section 5.5.1
 536          */
 537         msleep(1);
 538
 539         /* Bring controller out of reset */
 540         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 541
 542         count = 50;
 543         while (! azx_readb(chip, GCTL) && --count)
 544                 msleep(1);
 545
 546         /* Brent Chartrand said to wait >= 540us for codecs to intialize */
 547         msleep(1);
 548
 549         /* check to see if controller is ready */
 550         if (! azx_readb(chip, GCTL)) {
 551                 snd_printd("azx_reset: controller not ready!\n");
 552                 return -EBUSY;
 553         }
 554
 555         /* detect codecs */
 556         if (! chip->codec_mask) {
 557                 chip->codec_mask = azx_readw(chip, STATESTS);
 558                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 559         }
 560
 561         return 0;
 562 }
 563
 564
 565 /*
 566  * Lowlevel interface
 567  */
 568
 569 /* enable interrupts */
 570 static void azx_int_enable(azx_t *chip)
 571 {
 572         /* enable controller CIE and GIE */
 573         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 574                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 575 }
 576
 577 /* disable interrupts */
 578 static void azx_int_disable(azx_t *chip)
 579 {
 580         int i;
 581
 582         /* disable interrupts in stream descriptor */
 583         for (i = 0; i < MAX_ICH6_DEV; i++) {
 584                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 585                 azx_sd_writeb(azx_dev, SD_CTL,
 586                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 587         }
 588
 589         /* disable SIE for all streams */
 590         azx_writeb(chip, INTCTL, 0);
 591
 592         /* disable controller CIE and GIE */
 593         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 594                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 595 }
 596
 597 /* clear interrupts */
 598 static void azx_int_clear(azx_t *chip)
 599 {
 600         int i;
 601
 602         /* clear stream status */
 603         for (i = 0; i < MAX_ICH6_DEV; i++) {
 604                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 605                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 606         }
 607
 608         /* clear STATESTS */
 609         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 610
 611         /* clear rirb status */
 612         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 613
 614         /* clear int status */
 615         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 616 }
 617
 618 /* start a stream */
 619 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
 620 {
 621         /* enable SIE */
 622         azx_writeb(chip, INTCTL,
 623                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 624         /* set DMA start and interrupt mask */
 625         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 626                       SD_CTL_DMA_START | SD_INT_MASK);
 627 }
 628
 629 /* stop a stream */
 630 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
 631 {
 632         /* stop DMA */
 633         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 634                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 635         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 636         /* disable SIE */
 637         azx_writeb(chip, INTCTL,
 638                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 639 }
 640
 641
 642 /*
 643  * initialize the chip
 644  */
 645 static void azx_init_chip(azx_t *chip)
 646 {
 647         unsigned char tcsel_reg;
 648
 649         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 650          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 651          * Ensuring these bits are 0 clears playback static on some HD Audio codecs
 652          */
 653         pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
 654         pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
 655
 656         /* reset controller */
 657         azx_reset(chip);
 658
 659         /* initialize interrupts */
 660         azx_int_clear(chip);
 661         azx_int_enable(chip);
 662
 663         /* initialize the codec command I/O */
 664         azx_init_cmd_io(chip);
 665
 666         if (chip->position_fix == POS_FIX_POSBUF) {
 667                 /* program the position buffer */
 668                 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 669                 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 670         }
 671 }
 672
 673
 674 /*
 675  * interrupt handler
 676  */
 677 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
 678 {
 679         azx_t *chip = dev_id;
 680         azx_dev_t *azx_dev;
 681         u32 status;
 682         int i;
 683
 684         spin_lock(&chip->reg_lock);
 685
 686         status = azx_readl(chip, INTSTS);
 687         if (status == 0) {
 688                 spin_unlock(&chip->reg_lock);
 689                 return IRQ_NONE;
 690         }
 691
 692         for (i = 0; i < MAX_ICH6_DEV; i++) {
 693                 azx_dev = &chip->azx_dev[i];
 694                 if (status & azx_dev->sd_int_sta_mask) {
 695                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 696                         if (azx_dev->substream && azx_dev->running) {
 697                                 spin_unlock(&chip->reg_lock);
 698                                 snd_pcm_period_elapsed(azx_dev->substream);
 699                                 spin_lock(&chip->reg_lock);
 700                         }
 701                 }
 702         }
 703
 704         /* clear rirb int */
 705         status = azx_readb(chip, RIRBSTS);
 706         if (status & RIRB_INT_MASK) {
 707                 if (status & RIRB_INT_RESPONSE)
 708                         azx_update_rirb(chip);
 709                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 710         }
 711
 712 #if 0
 713         /* clear state status int */
 714         if (azx_readb(chip, STATESTS) & 0x04)
 715                 azx_writeb(chip, STATESTS, 0x04);
 716 #endif
 717         spin_unlock(&chip->reg_lock);
 718
 719         return IRQ_HANDLED;
 720 }
 721
 722
 723 /*
 724  * set up BDL entries
 725  */
 726 static void azx_setup_periods(azx_dev_t *azx_dev)
 727 {
 728         u32 *bdl = azx_dev->bdl;
 729         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 730         int idx;
 731
 732         /* reset BDL address */
 733         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 734         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 735
 736         /* program the initial BDL entries */
 737         for (idx = 0; idx < azx_dev->frags; idx++) {
 738                 unsigned int off = idx << 2; /* 4 dword step */
 739                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 740                 /* program the address field of the BDL entry */
 741                 bdl[off] = cpu_to_le32((u32)addr);
 742                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 743
 744                 /* program the size field of the BDL entry */
 745                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 746
 747                 /* program the IOC to enable interrupt when buffer completes */
 748                 bdl[off+3] = cpu_to_le32(0x01);
 749         }
 750 }
 751
 752 /*
 753  * set up the SD for streaming
 754  */
 755 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
 756 {
 757         unsigned char val;
 758         int timeout;
 759
 760         /* make sure the run bit is zero for SD */
 761         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 762         /* reset stream */
 763         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 764         udelay(3);
 765         timeout = 300;
 766         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 767                --timeout)
 768                 ;
 769         val &= ~SD_CTL_STREAM_RESET;
 770         azx_sd_writeb(azx_dev, SD_CTL, val);
 771         udelay(3);
 772
 773         timeout = 300;
 774         /* waiting for hardware to report that the stream is out of reset */
 775         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 776                --timeout)
 777                 ;
 778
 779         /* program the stream_tag */
 780         azx_sd_writel(azx_dev, SD_CTL,
 781                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
 782                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
 783
 784         /* program the length of samples in cyclic buffer */
 785         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 786
 787         /* program the stream format */
 788         /* this value needs to be the same as the one programmed */
 789         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 790
 791         /* program the stream LVI (last valid index) of the BDL */
 792         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 793
 794         /* program the BDL address */
 795         /* lower BDL address */
 796         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
 797         /* upper BDL address */
 798         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
 799
 800         if (chip->position_fix == POS_FIX_POSBUF) {
 801                 /* enable the position buffer */
 802                 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
 803                         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
 804         }
 805
 806         /* set the interrupt enable bits in the descriptor control register */
 807         azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
 808
 809         return 0;
 810 }
 811
 812
 813 /*
 814  * Codec initialization
 815  */
 816
 817 static int __devinit azx_codec_create(azx_t *chip, const char *model)
 818 {
 819         struct hda_bus_template bus_temp;
 820         int c, codecs, err;
 821
 822         memset(&bus_temp, 0, sizeof(bus_temp));
 823         bus_temp.private_data = chip;
 824         bus_temp.modelname = model;
 825         bus_temp.pci = chip->pci;
 826         bus_temp.ops.command = azx_send_cmd;
 827         bus_temp.ops.get_response = azx_get_response;
 828
 829         if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
 830                 return err;
 831
 832         codecs = 0;
 833         for (c = 0; c < AZX_MAX_CODECS; c++) {
 834                 if (chip->codec_mask & (1 << c)) {
 835                         err = snd_hda_codec_new(chip->bus, c, NULL);
 836                         if (err < 0)
 837                                 continue;
 838                         codecs++;
 839                 }
 840         }
 841         if (! codecs) {
 842                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
 843                 return -ENXIO;
 844         }
 845
 846         return 0;
 847 }
 848
 849
 850 /*
 851  * PCM support
 852  */
 853
 854 /* assign a stream for the PCM */
 855 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
 856 {
 857         int dev, i;
 858         dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
 859         for (i = 0; i < 4; i++, dev++)
 860                 if (! chip->azx_dev[dev].opened) {
 861                         chip->azx_dev[dev].opened = 1;
 862                         return &chip->azx_dev[dev];
 863                 }
 864         return NULL;
 865 }
 866
 867 /* release the assigned stream */
 868 static inline void azx_release_device(azx_dev_t *azx_dev)
 869 {
 870         azx_dev->opened = 0;
 871 }
 872
 873 static snd_pcm_hardware_t azx_pcm_hw = {
 874         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 875                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 876                                  SNDRV_PCM_INFO_MMAP_VALID |
 877                                  SNDRV_PCM_INFO_PAUSE |
 878                                  SNDRV_PCM_INFO_RESUME),
 879         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 880         .rates =                SNDRV_PCM_RATE_48000,
 881         .rate_min =             48000,
 882         .rate_max =             48000,
 883         .channels_min =         2,
 884         .channels_max =         2,
 885         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 886         .period_bytes_min =     128,
 887         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 888         .periods_min =          2,
 889         .periods_max =          AZX_MAX_FRAG,
 890         .fifo_size =            0,
 891 };
 892
 893 struct azx_pcm {
 894         azx_t *chip;
 895         struct hda_codec *codec;
 896         struct hda_pcm_stream *hinfo[2];
 897 };
 898
 899 static int azx_pcm_open(snd_pcm_substream_t *substream)
 900 {
 901         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 902         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 903         azx_t *chip = apcm->chip;
 904         azx_dev_t *azx_dev;
 905         snd_pcm_runtime_t *runtime = substream->runtime;
 906         unsigned long flags;
 907         int err;
 908
 909         down(&chip->open_mutex);
 910         azx_dev = azx_assign_device(chip, substream->stream);
 911         if (azx_dev == NULL) {
 912                 up(&chip->open_mutex);
 913                 return -EBUSY;
 914         }
 915         runtime->hw = azx_pcm_hw;
 916         runtime->hw.channels_min = hinfo->channels_min;
 917         runtime->hw.channels_max = hinfo->channels_max;
 918         runtime->hw.formats = hinfo->formats;
 919         runtime->hw.rates = hinfo->rates;
 920         snd_pcm_limit_hw_rates(runtime);
 921         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 922         if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
 923                 azx_release_device(azx_dev);
 924                 up(&chip->open_mutex);
 925                 return err;
 926         }
 927         spin_lock_irqsave(&chip->reg_lock, flags);
 928         azx_dev->substream = substream;
 929         azx_dev->running = 0;
 930         spin_unlock_irqrestore(&chip->reg_lock, flags);
 931
 932         runtime->private_data = azx_dev;
 933         up(&chip->open_mutex);
 934         return 0;
 935 }
 936
 937 static int azx_pcm_close(snd_pcm_substream_t *substream)
 938 {
 939         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 940         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 941         azx_t *chip = apcm->chip;
 942         azx_dev_t *azx_dev = get_azx_dev(substream);
 943         unsigned long flags;
 944
 945         down(&chip->open_mutex);
 946         spin_lock_irqsave(&chip->reg_lock, flags);
 947         azx_dev->substream = NULL;
 948         azx_dev->running = 0;
 949         spin_unlock_irqrestore(&chip->reg_lock, flags);
 950         azx_release_device(azx_dev);
 951         hinfo->ops.close(hinfo, apcm->codec, substream);
 952         up(&chip->open_mutex);
 953         return 0;
 954 }
 955
 956 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
 957 {
 958         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 959 }
 960
 961 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
 962 {
 963         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 964         azx_dev_t *azx_dev = get_azx_dev(substream);
 965         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 966
 967         /* reset BDL address */
 968         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 969         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 970         azx_sd_writel(azx_dev, SD_CTL, 0);
 971
 972         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
 973
 974         return snd_pcm_lib_free_pages(substream);
 975 }
 976
 977 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
 978 {
 979         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 980         azx_t *chip = apcm->chip;
 981         azx_dev_t *azx_dev = get_azx_dev(substream);
 982         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 983         snd_pcm_runtime_t *runtime = substream->runtime;
 984
 985         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
 986         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
 987         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
 988         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
 989                                                          runtime->channels,
 990                                                          runtime->format,
 991                                                          hinfo->maxbps);
 992         if (! azx_dev->format_val) {
 993                 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
 994                            runtime->rate, runtime->channels, runtime->format);
 995                 return -EINVAL;
 996         }
 997
 998         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
 999                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1000         azx_setup_periods(azx_dev);
1001         azx_setup_controller(chip, azx_dev);
1002         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1003                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1004         else
1005                 azx_dev->fifo_size = 0;
1006
1007         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1008                                   azx_dev->format_val, substream);
1009 }
1010
1011 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1012 {
1013         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1014         azx_dev_t *azx_dev = get_azx_dev(substream);
1015         azx_t *chip = apcm->chip;
1016         int err = 0;
1017
1018         spin_lock(&chip->reg_lock);
1019         switch (cmd) {
1020         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1021         case SNDRV_PCM_TRIGGER_RESUME:
1022         case SNDRV_PCM_TRIGGER_START:
1023                 azx_stream_start(chip, azx_dev);
1024                 azx_dev->running = 1;
1025                 break;
1026         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1027         case SNDRV_PCM_TRIGGER_STOP:
1028                 azx_stream_stop(chip, azx_dev);
1029                 azx_dev->running = 0;
1030                 break;
1031         default:
1032                 err = -EINVAL;
1033         }
1034         spin_unlock(&chip->reg_lock);
1035         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1036             cmd == SNDRV_PCM_TRIGGER_STOP) {
1037                 int timeout = 5000;
1038                 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1039                         ;
1040         }
1041         return err;
1042 }
1043
1044 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1045 {
1046         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1047         azx_t *chip = apcm->chip;
1048         azx_dev_t *azx_dev = get_azx_dev(substream);
1049         unsigned int pos;
1050
1051         if (chip->position_fix == POS_FIX_POSBUF) {
1052                 /* use the position buffer */
1053                 pos = *azx_dev->posbuf;
1054         } else {
1055                 /* read LPIB */
1056                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1057                 if (chip->position_fix == POS_FIX_FIFO)
1058                         pos += azx_dev->fifo_size;
1059         }
1060         if (pos >= azx_dev->bufsize)
1061                 pos = 0;
1062         return bytes_to_frames(substream->runtime, pos);
1063 }
1064
1065 static snd_pcm_ops_t azx_pcm_ops = {
1066         .open = azx_pcm_open,
1067         .close = azx_pcm_close,
1068         .ioctl = snd_pcm_lib_ioctl,
1069         .hw_params = azx_pcm_hw_params,
1070         .hw_free = azx_pcm_hw_free,
1071         .prepare = azx_pcm_prepare,
1072         .trigger = azx_pcm_trigger,
1073         .pointer = azx_pcm_pointer,
1074 };
1075
1076 static void azx_pcm_free(snd_pcm_t *pcm)
1077 {
1078         kfree(pcm->private_data);
1079 }
1080
1081 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1082                                       struct hda_pcm *cpcm, int pcm_dev)
1083 {
1084         int err;
1085         snd_pcm_t *pcm;
1086         struct azx_pcm *apcm;
1087
1088         snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1089         snd_assert(cpcm->name, return -EINVAL);
1090
1091         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1092                           cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1093                           &pcm);
1094         if (err < 0)
1095                 return err;
1096         strcpy(pcm->name, cpcm->name);
1097         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1098         if (apcm == NULL)
1099                 return -ENOMEM;
1100         apcm->chip = chip;
1101         apcm->codec = codec;
1102         apcm->hinfo[0] = &cpcm->stream[0];
1103         apcm->hinfo[1] = &cpcm->stream[1];
1104         pcm->private_data = apcm;
1105         pcm->private_free = azx_pcm_free;
1106         if (cpcm->stream[0].substreams)
1107                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1108         if (cpcm->stream[1].substreams)
1109                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1110         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1111                                               snd_dma_pci_data(chip->pci),
1112                                               1024 * 64, 1024 * 128);
1113         chip->pcm[pcm_dev] = pcm;
1114
1115         return 0;
1116 }
1117
1118 static int __devinit azx_pcm_create(azx_t *chip)
1119 {
1120         struct list_head *p;
1121         struct hda_codec *codec;
1122         int c, err;
1123         int pcm_dev;
1124
1125         if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1126                 return err;
1127
1128         pcm_dev = 0;
1129         list_for_each(p, &chip->bus->codec_list) {
1130                 codec = list_entry(p, struct hda_codec, list);
1131                 for (c = 0; c < codec->num_pcms; c++) {
1132                         if (pcm_dev >= AZX_MAX_PCMS) {
1133                                 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1134                                 return -EINVAL;
1135                         }
1136                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1137                         if (err < 0)
1138                                 return err;
1139                         pcm_dev++;
1140                 }
1141         }
1142         return 0;
1143 }
1144
1145 /*
1146  * mixer creation - all stuff is implemented in hda module
1147  */
1148 static int __devinit azx_mixer_create(azx_t *chip)
1149 {
1150         return snd_hda_build_controls(chip->bus);
1151 }
1152
1153
1154 /*
1155  * initialize SD streams
1156  */
1157 static int __devinit azx_init_stream(azx_t *chip)
1158 {
1159         int i;
1160
1161         /* initialize each stream (aka device)
1162          * assign the starting bdl address to each stream (device) and initialize
1163          */
1164         for (i = 0; i < MAX_ICH6_DEV; i++) {
1165                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1166                 azx_dev_t *azx_dev = &chip->azx_dev[i];
1167                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1168                 azx_dev->bdl_addr = chip->bdl.addr + off;
1169                 if (chip->position_fix == POS_FIX_POSBUF)
1170                         azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1171                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1172                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1173                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1174                 azx_dev->sd_int_sta_mask = 1 << i;
1175                 /* stream tag: must be non-zero and unique */
1176                 azx_dev->index = i;
1177                 azx_dev->stream_tag = i + 1;
1178         }
1179
1180         return 0;
1181 }
1182
1183
1184 #ifdef CONFIG_PM
1185 /*
1186  * power management
1187  */
1188 static int azx_suspend(snd_card_t *card, pm_message_t state)
1189 {
1190         azx_t *chip = card->pm_private_data;
1191         int i;
1192
1193         for (i = 0; i < chip->pcm_devs; i++)
1194                 if (chip->pcm[i])
1195                         snd_pcm_suspend_all(chip->pcm[i]);
1196         snd_hda_suspend(chip->bus, state);
1197         azx_free_cmd_io(chip);
1198         pci_disable_device(chip->pci);
1199         return 0;
1200 }
1201
1202 static int azx_resume(snd_card_t *card)
1203 {
1204         azx_t *chip = card->pm_private_data;
1205
1206         pci_enable_device(chip->pci);
1207         pci_set_master(chip->pci);
1208         azx_init_chip(chip);
1209         snd_hda_resume(chip->bus);
1210         return 0;
1211 }
1212 #endif /* CONFIG_PM */
1213
1214
1215 /*
1216  * destructor
1217  */
1218 static int azx_free(azx_t *chip)
1219 {
1220         if (chip->remap_addr) {
1221                 int i;
1222
1223                 for (i = 0; i < MAX_ICH6_DEV; i++)
1224                         azx_stream_stop(chip, &chip->azx_dev[i]);
1225
1226                 /* disable interrupts */
1227                 azx_int_disable(chip);
1228                 azx_int_clear(chip);
1229
1230                 /* disable CORB/RIRB */
1231                 azx_free_cmd_io(chip);
1232
1233                 /* disable position buffer */
1234                 azx_writel(chip, DPLBASE, 0);
1235                 azx_writel(chip, DPUBASE, 0);
1236
1237                 /* wait a little for interrupts to finish */
1238                 msleep(1);
1239
1240                 iounmap(chip->remap_addr);
1241         }
1242
1243         if (chip->irq >= 0)
1244                 free_irq(chip->irq, (void*)chip);
1245
1246         if (chip->bdl.area)
1247                 snd_dma_free_pages(&chip->bdl);
1248         if (chip->rb.area)
1249                 snd_dma_free_pages(&chip->rb);
1250         if (chip->posbuf.area)
1251                 snd_dma_free_pages(&chip->posbuf);
1252         pci_release_regions(chip->pci);
1253         pci_disable_device(chip->pci);
1254         kfree(chip);
1255
1256         return 0;
1257 }
1258
1259 static int azx_dev_free(snd_device_t *device)
1260 {
1261         return azx_free(device->device_data);
1262 }
1263
1264 /*
1265  * constructor
1266  */
1267 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
1268                                 int posfix, azx_t **rchip)
1269 {
1270         azx_t *chip;
1271         int err = 0;
1272         static snd_device_ops_t ops = {
1273                 .dev_free = azx_dev_free,
1274         };
1275
1276         *rchip = NULL;
1277
1278         if ((err = pci_enable_device(pci)) < 0)
1279                 return err;
1280
1281         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1282
1283         if (NULL == chip) {
1284                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1285                 pci_disable_device(pci);
1286                 return -ENOMEM;
1287         }
1288
1289         spin_lock_init(&chip->reg_lock);
1290         init_MUTEX(&chip->open_mutex);
1291         chip->card = card;
1292         chip->pci = pci;
1293         chip->irq = -1;
1294
1295         chip->position_fix = posfix;
1296
1297         if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1298                 kfree(chip);
1299                 pci_disable_device(pci);
1300                 return err;
1301         }
1302
1303         chip->addr = pci_resource_start(pci,0);
1304         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1305         if (chip->remap_addr == NULL) {
1306                 snd_printk(KERN_ERR SFX "ioremap error\n");
1307                 err = -ENXIO;
1308                 goto errout;
1309         }
1310
1311         if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1312                         "HDA Intel", (void*)chip)) {
1313                 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1314                 err = -EBUSY;
1315                 goto errout;
1316         }
1317         chip->irq = pci->irq;
1318
1319         pci_set_master(pci);
1320         synchronize_irq(chip->irq);
1321
1322         /* allocate memory for the BDL for each stream */
1323         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1324                                        PAGE_SIZE, &chip->bdl)) < 0) {
1325                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1326                 goto errout;
1327         }
1328         if (chip->position_fix == POS_FIX_POSBUF) {
1329                 /* allocate memory for the position buffer */
1330                 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1331                                                MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
1332                         snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1333                         goto errout;
1334                 }
1335         }
1336         /* allocate CORB/RIRB */
1337         if ((err = azx_alloc_cmd_io(chip)) < 0)
1338                 goto errout;
1339
1340         /* initialize streams */
1341         azx_init_stream(chip);
1342
1343         /* initialize chip */
1344         azx_init_chip(chip);
1345
1346         /* codec detection */
1347         if (! chip->codec_mask) {
1348                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1349                 err = -ENODEV;
1350                 goto errout;
1351         }
1352
1353         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1354                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1355                 goto errout;
1356         }
1357
1358         *rchip = chip;
1359         return 0;
1360
1361  errout:
1362         azx_free(chip);
1363         return err;
1364 }
1365
1366 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1367 {
1368         static int dev;
1369         snd_card_t *card;
1370         azx_t *chip;
1371         int err = 0;
1372
1373         if (dev >= SNDRV_CARDS)
1374                 return -ENODEV;
1375         if (! enable[dev]) {
1376                 dev++;
1377                 return -ENOENT;
1378         }
1379
1380         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1381         if (NULL == card) {
1382                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1383                 return -ENOMEM;
1384         }
1385
1386         if ((err = azx_create(card, pci, position_fix[dev], &chip)) < 0) {
1387                 snd_card_free(card);
1388                 return err;
1389         }
1390
1391         strcpy(card->driver, "HDA-Intel");
1392         strcpy(card->shortname, "HDA Intel");
1393         sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1394
1395         /* create codec instances */
1396         if ((err = azx_codec_create(chip, model[dev])) < 0) {
1397                 snd_card_free(card);
1398                 return err;
1399         }
1400
1401         /* create PCM streams */
1402         if ((err = azx_pcm_create(chip)) < 0) {
1403                 snd_card_free(card);
1404                 return err;
1405         }
1406
1407         /* create mixer controls */
1408         if ((err = azx_mixer_create(chip)) < 0) {
1409                 snd_card_free(card);
1410                 return err;
1411         }
1412
1413         snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1414         snd_card_set_dev(card, &pci->dev);
1415
1416         if ((err = snd_card_register(card)) < 0) {
1417                 snd_card_free(card);
1418                 return err;
1419         }
1420
1421         pci_set_drvdata(pci, card);
1422         dev++;
1423
1424         return err;
1425 }
1426
1427 static void __devexit azx_remove(struct pci_dev *pci)
1428 {
1429         snd_card_free(pci_get_drvdata(pci));
1430         pci_set_drvdata(pci, NULL);
1431 }
1432
1433 /* PCI IDs */
1434 static struct pci_device_id azx_ids[] = {
1435         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
1436         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
1437         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
1438         { 0, }
1439 };
1440 MODULE_DEVICE_TABLE(pci, azx_ids);
1441
1442 /* pci_driver definition */
1443 static struct pci_driver driver = {
1444         .name = "HDA Intel",
1445         .id_table = azx_ids,
1446         .probe = azx_probe,
1447         .remove = __devexit_p(azx_remove),
1448         SND_PCI_PM_CALLBACKS
1449 };
1450
1451 static int __init alsa_card_azx_init(void)
1452 {
1453         return pci_register_driver(&driver);
1454 }
1455
1456 static void __exit alsa_card_azx_exit(void)
1457 {
1458         pci_unregister_driver(&driver);
1459 }
1460
1461 module_init(alsa_card_azx_init)
1462 module_exit(alsa_card_azx_exit)