err.no Git - linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <sound/core.h>
  49 #include <sound/initval.h>
  50 #include "hda_codec.h"
  51
  52
  53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  56 static char *model[SNDRV_CARDS];
  57 static int position_fix[SNDRV_CARDS];
  58 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  59 static int single_cmd;
  60 static int enable_msi;
  61
  62 module_param_array(index, int, NULL, 0444);
  63 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  64 module_param_array(id, charp, NULL, 0444);
  65 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  66 module_param_array(enable, bool, NULL, 0444);
  67 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  68 module_param_array(model, charp, NULL, 0444);
  69 MODULE_PARM_DESC(model, "Use the given board model.");
  70 module_param_array(position_fix, int, NULL, 0444);
  71 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  72                  "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
  73 module_param_array(probe_mask, int, NULL, 0444);
  74 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  75 module_param(single_cmd, bool, 0444);
  76 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  77                  "(for debugging only).");
  78 module_param(enable_msi, int, 0444);
  79 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  80
  81 #ifdef CONFIG_SND_HDA_POWER_SAVE
  82 /* power_save option is defined in hda_codec.c */
  83
  84 /* reset the HD-audio controller in power save mode.
  85  * this may give more power-saving, but will take longer time to
  86  * wake up.
  87  */
  88 static int power_save_controller = 1;
  89 module_param(power_save_controller, bool, 0644);
  90 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  91 #endif
  92
  93 MODULE_LICENSE("GPL");
  94 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  95                          "{Intel, ICH6M},"
  96                          "{Intel, ICH7},"
  97                          "{Intel, ESB2},"
  98                          "{Intel, ICH8},"
  99                          "{Intel, ICH9},"
 100                          "{Intel, ICH10},"
 101                          "{Intel, SCH},"
 102                          "{ATI, SB450},"
 103                          "{ATI, SB600},"
 104                          "{ATI, RS600},"
 105                          "{ATI, RS690},"
 106                          "{ATI, RS780},"
 107                          "{ATI, R600},"
 108                          "{ATI, RV630},"
 109                          "{ATI, RV610},"
 110                          "{ATI, RV670},"
 111                          "{ATI, RV635},"
 112                          "{ATI, RV620},"
 113                          "{ATI, RV770},"
 114                          "{VIA, VT8251},"
 115                          "{VIA, VT8237A},"
 116                          "{SiS, SIS966},"
 117                          "{ULI, M5461}}");
 118 MODULE_DESCRIPTION("Intel HDA driver");
 119
 120 #define SFX     "hda-intel: "
 121
 122
 123 /*
 124  * registers
 125  */
 126 #define ICH6_REG_GCAP                   0x00
 127 #define ICH6_REG_VMIN                   0x02
 128 #define ICH6_REG_VMAJ                   0x03
 129 #define ICH6_REG_OUTPAY                 0x04
 130 #define ICH6_REG_INPAY                  0x06
 131 #define ICH6_REG_GCTL                   0x08
 132 #define ICH6_REG_WAKEEN                 0x0c
 133 #define ICH6_REG_STATESTS               0x0e
 134 #define ICH6_REG_GSTS                   0x10
 135 #define ICH6_REG_INTCTL                 0x20
 136 #define ICH6_REG_INTSTS                 0x24
 137 #define ICH6_REG_WALCLK                 0x30
 138 #define ICH6_REG_SYNC                   0x34
 139 #define ICH6_REG_CORBLBASE              0x40
 140 #define ICH6_REG_CORBUBASE              0x44
 141 #define ICH6_REG_CORBWP                 0x48
 142 #define ICH6_REG_CORBRP                 0x4A
 143 #define ICH6_REG_CORBCTL                0x4c
 144 #define ICH6_REG_CORBSTS                0x4d
 145 #define ICH6_REG_CORBSIZE               0x4e
 146
 147 #define ICH6_REG_RIRBLBASE              0x50
 148 #define ICH6_REG_RIRBUBASE              0x54
 149 #define ICH6_REG_RIRBWP                 0x58
 150 #define ICH6_REG_RINTCNT                0x5a
 151 #define ICH6_REG_RIRBCTL                0x5c
 152 #define ICH6_REG_RIRBSTS                0x5d
 153 #define ICH6_REG_RIRBSIZE               0x5e
 154
 155 #define ICH6_REG_IC                     0x60
 156 #define ICH6_REG_IR                     0x64
 157 #define ICH6_REG_IRS                    0x68
 158 #define   ICH6_IRS_VALID        (1<<1)
 159 #define   ICH6_IRS_BUSY         (1<<0)
 160
 161 #define ICH6_REG_DPLBASE                0x70
 162 #define ICH6_REG_DPUBASE                0x74
 163 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 164
 165 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 166 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 167
 168 /* stream register offsets from stream base */
 169 #define ICH6_REG_SD_CTL                 0x00
 170 #define ICH6_REG_SD_STS                 0x03
 171 #define ICH6_REG_SD_LPIB                0x04
 172 #define ICH6_REG_SD_CBL                 0x08
 173 #define ICH6_REG_SD_LVI                 0x0c
 174 #define ICH6_REG_SD_FIFOW               0x0e
 175 #define ICH6_REG_SD_FIFOSIZE            0x10
 176 #define ICH6_REG_SD_FORMAT              0x12
 177 #define ICH6_REG_SD_BDLPL               0x18
 178 #define ICH6_REG_SD_BDLPU               0x1c
 179
 180 /* PCI space */
 181 #define ICH6_PCIREG_TCSEL       0x44
 182
 183 /*
 184  * other constants
 185  */
 186
 187 /* max number of SDs */
 188 /* ICH, ATI and VIA have 4 playback and 4 capture */
 189 #define ICH6_NUM_CAPTURE        4
 190 #define ICH6_NUM_PLAYBACK       4
 191
 192 /* ULI has 6 playback and 5 capture */
 193 #define ULI_NUM_CAPTURE         5
 194 #define ULI_NUM_PLAYBACK        6
 195
 196 /* ATI HDMI has 1 playback and 0 capture */
 197 #define ATIHDMI_NUM_CAPTURE     0
 198 #define ATIHDMI_NUM_PLAYBACK    1
 199
 200 /* this number is statically defined for simplicity */
 201 #define MAX_AZX_DEV             16
 202
 203 /* max number of fragments - we may use more if allocating more pages for BDL */
 204 #define BDL_SIZE                4096
 205 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 206 #define AZX_MAX_FRAG            32
 207 /* max buffer size - no h/w limit, you can increase as you like */
 208 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 209 /* max number of PCM devics per card */
 210 #define AZX_MAX_PCMS            8
 211
 212 /* RIRB int mask: overrun[2], response[0] */
 213 #define RIRB_INT_RESPONSE       0x01
 214 #define RIRB_INT_OVERRUN        0x04
 215 #define RIRB_INT_MASK           0x05
 216
 217 /* STATESTS int mask: SD2,SD1,SD0 */
 218 #define AZX_MAX_CODECS          3
 219 #define STATESTS_INT_MASK       0x07
 220
 221 /* SD_CTL bits */
 222 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 223 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 224 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 225 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 226 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 227 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 228 #define SD_CTL_STREAM_TAG_SHIFT 20
 229
 230 /* SD_CTL and SD_STS */
 231 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 232 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 233 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 234 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 235                                  SD_INT_COMPLETE)
 236
 237 /* SD_STS */
 238 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 239
 240 /* INTCTL and INTSTS */
 241 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 242 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 243 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 244
 245 /* GCTL unsolicited response enable bit */
 246 #define ICH6_GCTL_UREN          (1<<8)
 247
 248 /* GCTL reset bit */
 249 #define ICH6_GCTL_RESET         (1<<0)
 250
 251 /* CORB/RIRB control, read/write pointer */
 252 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 253 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 254 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 255 /* below are so far hardcoded - should read registers in future */
 256 #define ICH6_MAX_CORB_ENTRIES   256
 257 #define ICH6_MAX_RIRB_ENTRIES   256
 258
 259 /* position fix mode */
 260 enum {
 261         POS_FIX_AUTO,
 262         POS_FIX_NONE,
 263         POS_FIX_POSBUF,
 264         POS_FIX_FIFO,
 265 };
 266
 267 /* Defines for ATI HD Audio support in SB450 south bridge */
 268 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 269 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 270
 271 /* Defines for Nvidia HDA support */
 272 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 273 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 274
 275 /* Defines for Intel SCH HDA snoop control */
 276 #define INTEL_SCH_HDA_DEVC      0x78
 277 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 278
 279
 280 /*
 281  */
 282
 283 struct azx_dev {
 284         struct snd_dma_buffer bdl; /* BDL buffer */
 285         u32 *posbuf;            /* position buffer pointer */
 286
 287         unsigned int bufsize;   /* size of the play buffer in bytes */
 288         unsigned int period_bytes; /* size of the period in bytes */
 289         unsigned int frags;     /* number for period in the play buffer */
 290         unsigned int fifo_size; /* FIFO size */
 291
 292         void __iomem *sd_addr;  /* stream descriptor pointer */
 293
 294         u32 sd_int_sta_mask;    /* stream int status mask */
 295
 296         /* pcm support */
 297         struct snd_pcm_substream *substream;    /* assigned substream,
 298                                                  * set in PCM open
 299                                                  */
 300         unsigned int format_val;        /* format value to be set in the
 301                                          * controller and the codec
 302                                          */
 303         unsigned char stream_tag;       /* assigned stream */
 304         unsigned char index;            /* stream index */
 305
 306         unsigned int opened :1;
 307         unsigned int running :1;
 308         unsigned int irq_pending: 1;
 309 };
 310
 311 /* CORB/RIRB */
 312 struct azx_rb {
 313         u32 *buf;               /* CORB/RIRB buffer
 314                                  * Each CORB entry is 4byte, RIRB is 8byte
 315                                  */
 316         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 317         /* for RIRB */
 318         unsigned short rp, wp;  /* read/write pointers */
 319         int cmds;               /* number of pending requests */
 320         u32 res;                /* last read value */
 321 };
 322
 323 struct azx {
 324         struct snd_card *card;
 325         struct pci_dev *pci;
 326
 327         /* chip type specific */
 328         int driver_type;
 329         int playback_streams;
 330         int playback_index_offset;
 331         int capture_streams;
 332         int capture_index_offset;
 333         int num_streams;
 334
 335         /* pci resources */
 336         unsigned long addr;
 337         void __iomem *remap_addr;
 338         int irq;
 339
 340         /* locks */
 341         spinlock_t reg_lock;
 342         struct mutex open_mutex;
 343
 344         /* streams (x num_streams) */
 345         struct azx_dev *azx_dev;
 346
 347         /* PCM */
 348         struct snd_pcm *pcm[AZX_MAX_PCMS];
 349
 350         /* HD codec */
 351         unsigned short codec_mask;
 352         struct hda_bus *bus;
 353
 354         /* CORB/RIRB */
 355         struct azx_rb corb;
 356         struct azx_rb rirb;
 357
 358         /* CORB/RIRB and position buffers */
 359         struct snd_dma_buffer rb;
 360         struct snd_dma_buffer posbuf;
 361
 362         /* flags */
 363         int position_fix;
 364         unsigned int running :1;
 365         unsigned int initialized :1;
 366         unsigned int single_cmd :1;
 367         unsigned int polling_mode :1;
 368         unsigned int msi :1;
 369
 370         /* for debugging */
 371         unsigned int last_cmd;  /* last issued command (to sync) */
 372
 373         /* for pending irqs */
 374         struct work_struct irq_pending_work;
 375 };
 376
 377 /* driver types */
 378 enum {
 379         AZX_DRIVER_ICH,
 380         AZX_DRIVER_SCH,
 381         AZX_DRIVER_ATI,
 382         AZX_DRIVER_ATIHDMI,
 383         AZX_DRIVER_VIA,
 384         AZX_DRIVER_SIS,
 385         AZX_DRIVER_ULI,
 386         AZX_DRIVER_NVIDIA,
 387 };
 388
 389 static char *driver_short_names[] __devinitdata = {
 390         [AZX_DRIVER_ICH] = "HDA Intel",
 391         [AZX_DRIVER_SCH] = "HDA Intel MID",
 392         [AZX_DRIVER_ATI] = "HDA ATI SB",
 393         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 394         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 395         [AZX_DRIVER_SIS] = "HDA SIS966",
 396         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 397         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 398 };
 399
 400 /*
 401  * macros for easy use
 402  */
 403 #define azx_writel(chip,reg,value) \
 404         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 405 #define azx_readl(chip,reg) \
 406         readl((chip)->remap_addr + ICH6_REG_##reg)
 407 #define azx_writew(chip,reg,value) \
 408         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 409 #define azx_readw(chip,reg) \
 410         readw((chip)->remap_addr + ICH6_REG_##reg)
 411 #define azx_writeb(chip,reg,value) \
 412         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 413 #define azx_readb(chip,reg) \
 414         readb((chip)->remap_addr + ICH6_REG_##reg)
 415
 416 #define azx_sd_writel(dev,reg,value) \
 417         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 418 #define azx_sd_readl(dev,reg) \
 419         readl((dev)->sd_addr + ICH6_REG_##reg)
 420 #define azx_sd_writew(dev,reg,value) \
 421         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 422 #define azx_sd_readw(dev,reg) \
 423         readw((dev)->sd_addr + ICH6_REG_##reg)
 424 #define azx_sd_writeb(dev,reg,value) \
 425         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 426 #define azx_sd_readb(dev,reg) \
 427         readb((dev)->sd_addr + ICH6_REG_##reg)
 428
 429 /* for pcm support */
 430 #define get_azx_dev(substream) (substream->runtime->private_data)
 431
 432 /* Get the upper 32bit of the given dma_addr_t
 433  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 434  */
 435 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 436
 437 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 438
 439 /*
 440  * Interface for HD codec
 441  */
 442
 443 /*
 444  * CORB / RIRB interface
 445  */
 446 static int azx_alloc_cmd_io(struct azx *chip)
 447 {
 448         int err;
 449
 450         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 451         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 452                                   snd_dma_pci_data(chip->pci),
 453                                   PAGE_SIZE, &chip->rb);
 454         if (err < 0) {
 455                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 456                 return err;
 457         }
 458         return 0;
 459 }
 460
 461 static void azx_init_cmd_io(struct azx *chip)
 462 {
 463         /* CORB set up */
 464         chip->corb.addr = chip->rb.addr;
 465         chip->corb.buf = (u32 *)chip->rb.area;
 466         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 467         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 468
 469         /* set the corb size to 256 entries (ULI requires explicitly) */
 470         azx_writeb(chip, CORBSIZE, 0x02);
 471         /* set the corb write pointer to 0 */
 472         azx_writew(chip, CORBWP, 0);
 473         /* reset the corb hw read pointer */
 474         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 475         /* enable corb dma */
 476         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 477
 478         /* RIRB set up */
 479         chip->rirb.addr = chip->rb.addr + 2048;
 480         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 481         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 482         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 483
 484         /* set the rirb size to 256 entries (ULI requires explicitly) */
 485         azx_writeb(chip, RIRBSIZE, 0x02);
 486         /* reset the rirb hw write pointer */
 487         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 488         /* set N=1, get RIRB response interrupt for new entry */
 489         azx_writew(chip, RINTCNT, 1);
 490         /* enable rirb dma and response irq */
 491         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 492         chip->rirb.rp = chip->rirb.cmds = 0;
 493 }
 494
 495 static void azx_free_cmd_io(struct azx *chip)
 496 {
 497         /* disable ringbuffer DMAs */
 498         azx_writeb(chip, RIRBCTL, 0);
 499         azx_writeb(chip, CORBCTL, 0);
 500 }
 501
 502 /* send a command */
 503 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 504 {
 505         struct azx *chip = codec->bus->private_data;
 506         unsigned int wp;
 507
 508         /* add command to corb */
 509         wp = azx_readb(chip, CORBWP);
 510         wp++;
 511         wp %= ICH6_MAX_CORB_ENTRIES;
 512
 513         spin_lock_irq(&chip->reg_lock);
 514         chip->rirb.cmds++;
 515         chip->corb.buf[wp] = cpu_to_le32(val);
 516         azx_writel(chip, CORBWP, wp);
 517         spin_unlock_irq(&chip->reg_lock);
 518
 519         return 0;
 520 }
 521
 522 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 523
 524 /* retrieve RIRB entry - called from interrupt handler */
 525 static void azx_update_rirb(struct azx *chip)
 526 {
 527         unsigned int rp, wp;
 528         u32 res, res_ex;
 529
 530         wp = azx_readb(chip, RIRBWP);
 531         if (wp == chip->rirb.wp)
 532                 return;
 533         chip->rirb.wp = wp;
 534
 535         while (chip->rirb.rp != wp) {
 536                 chip->rirb.rp++;
 537                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 538
 539                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 540                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 541                 res = le32_to_cpu(chip->rirb.buf[rp]);
 542                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 543                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 544                 else if (chip->rirb.cmds) {
 545                         chip->rirb.res = res;
 546                         smp_wmb();
 547                         chip->rirb.cmds--;
 548                 }
 549         }
 550 }
 551
 552 /* receive a response */
 553 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 554 {
 555         struct azx *chip = codec->bus->private_data;
 556         unsigned long timeout;
 557
 558  again:
 559         timeout = jiffies + msecs_to_jiffies(1000);
 560         for (;;) {
 561                 if (chip->polling_mode) {
 562                         spin_lock_irq(&chip->reg_lock);
 563                         azx_update_rirb(chip);
 564                         spin_unlock_irq(&chip->reg_lock);
 565                 }
 566                 if (!chip->rirb.cmds) {
 567                         smp_rmb();
 568                         return chip->rirb.res; /* the last value */
 569                 }
 570                 if (time_after(jiffies, timeout))
 571                         break;
 572                 if (codec->bus->needs_damn_long_delay)
 573                         msleep(2); /* temporary workaround */
 574                 else {
 575                         udelay(10);
 576                         cond_resched();
 577                 }
 578         }
 579
 580         if (chip->msi) {
 581                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 582                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 583                 free_irq(chip->irq, chip);
 584                 chip->irq = -1;
 585                 pci_disable_msi(chip->pci);
 586                 chip->msi = 0;
 587                 if (azx_acquire_irq(chip, 1) < 0)
 588                         return -1;
 589                 goto again;
 590         }
 591
 592         if (!chip->polling_mode) {
 593                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 594                            "switching to polling mode: last cmd=0x%08x\n",
 595                            chip->last_cmd);
 596                 chip->polling_mode = 1;
 597                 goto again;
 598         }
 599
 600         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 601                    "switching to single_cmd mode: last cmd=0x%08x\n",
 602                    chip->last_cmd);
 603         chip->rirb.rp = azx_readb(chip, RIRBWP);
 604         chip->rirb.cmds = 0;
 605         /* switch to single_cmd mode */
 606         chip->single_cmd = 1;
 607         azx_free_cmd_io(chip);
 608         return -1;
 609 }
 610
 611 /*
 612  * Use the single immediate command instead of CORB/RIRB for simplicity
 613  *
 614  * Note: according to Intel, this is not preferred use.  The command was
 615  *       intended for the BIOS only, and may get confused with unsolicited
 616  *       responses.  So, we shouldn't use it for normal operation from the
 617  *       driver.
 618  *       I left the codes, however, for debugging/testing purposes.
 619  */
 620
 621 /* send a command */
 622 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 623 {
 624         struct azx *chip = codec->bus->private_data;
 625         int timeout = 50;
 626
 627         while (timeout--) {
 628                 /* check ICB busy bit */
 629                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 630                         /* Clear IRV valid bit */
 631                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 632                                    ICH6_IRS_VALID);
 633                         azx_writel(chip, IC, val);
 634                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 635                                    ICH6_IRS_BUSY);
 636                         return 0;
 637                 }
 638                 udelay(1);
 639         }
 640         if (printk_ratelimit())
 641                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 642                            azx_readw(chip, IRS), val);
 643         return -EIO;
 644 }
 645
 646 /* receive a response */
 647 static unsigned int azx_single_get_response(struct hda_codec *codec)
 648 {
 649         struct azx *chip = codec->bus->private_data;
 650         int timeout = 50;
 651
 652         while (timeout--) {
 653                 /* check IRV busy bit */
 654                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 655                         return azx_readl(chip, IR);
 656                 udelay(1);
 657         }
 658         if (printk_ratelimit())
 659                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 660                            azx_readw(chip, IRS));
 661         return (unsigned int)-1;
 662 }
 663
 664 /*
 665  * The below are the main callbacks from hda_codec.
 666  *
 667  * They are just the skeleton to call sub-callbacks according to the
 668  * current setting of chip->single_cmd.
 669  */
 670
 671 /* send a command */
 672 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 673                         int direct, unsigned int verb,
 674                         unsigned int para)
 675 {
 676         struct azx *chip = codec->bus->private_data;
 677         u32 val;
 678
 679         val = (u32)(codec->addr & 0x0f) << 28;
 680         val |= (u32)direct << 27;
 681         val |= (u32)nid << 20;
 682         val |= verb << 8;
 683         val |= para;
 684         chip->last_cmd = val;
 685
 686         if (chip->single_cmd)
 687                 return azx_single_send_cmd(codec, val);
 688         else
 689                 return azx_corb_send_cmd(codec, val);
 690 }
 691
 692 /* get a response */
 693 static unsigned int azx_get_response(struct hda_codec *codec)
 694 {
 695         struct azx *chip = codec->bus->private_data;
 696         if (chip->single_cmd)
 697                 return azx_single_get_response(codec);
 698         else
 699                 return azx_rirb_get_response(codec);
 700 }
 701
 702 #ifdef CONFIG_SND_HDA_POWER_SAVE
 703 static void azx_power_notify(struct hda_codec *codec);
 704 #endif
 705
 706 /* reset codec link */
 707 static int azx_reset(struct azx *chip)
 708 {
 709         int count;
 710
 711         /* clear STATESTS */
 712         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 713
 714         /* reset controller */
 715         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 716
 717         count = 50;
 718         while (azx_readb(chip, GCTL) && --count)
 719                 msleep(1);
 720
 721         /* delay for >= 100us for codec PLL to settle per spec
 722          * Rev 0.9 section 5.5.1
 723          */
 724         msleep(1);
 725
 726         /* Bring controller out of reset */
 727         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 728
 729         count = 50;
 730         while (!azx_readb(chip, GCTL) && --count)
 731                 msleep(1);
 732
 733         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 734         msleep(1);
 735
 736         /* check to see if controller is ready */
 737         if (!azx_readb(chip, GCTL)) {
 738                 snd_printd("azx_reset: controller not ready!\n");
 739                 return -EBUSY;
 740         }
 741
 742         /* Accept unsolicited responses */
 743         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 744
 745         /* detect codecs */
 746         if (!chip->codec_mask) {
 747                 chip->codec_mask = azx_readw(chip, STATESTS);
 748                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 749         }
 750
 751         return 0;
 752 }
 753
 754
 755 /*
 756  * Lowlevel interface
 757  */
 758
 759 /* enable interrupts */
 760 static void azx_int_enable(struct azx *chip)
 761 {
 762         /* enable controller CIE and GIE */
 763         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 764                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 765 }
 766
 767 /* disable interrupts */
 768 static void azx_int_disable(struct azx *chip)
 769 {
 770         int i;
 771
 772         /* disable interrupts in stream descriptor */
 773         for (i = 0; i < chip->num_streams; i++) {
 774                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 775                 azx_sd_writeb(azx_dev, SD_CTL,
 776                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 777         }
 778
 779         /* disable SIE for all streams */
 780         azx_writeb(chip, INTCTL, 0);
 781
 782         /* disable controller CIE and GIE */
 783         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 784                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 785 }
 786
 787 /* clear interrupts */
 788 static void azx_int_clear(struct azx *chip)
 789 {
 790         int i;
 791
 792         /* clear stream status */
 793         for (i = 0; i < chip->num_streams; i++) {
 794                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 795                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 796         }
 797
 798         /* clear STATESTS */
 799         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 800
 801         /* clear rirb status */
 802         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 803
 804         /* clear int status */
 805         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 806 }
 807
 808 /* start a stream */
 809 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 810 {
 811         /* enable SIE */
 812         azx_writeb(chip, INTCTL,
 813                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 814         /* set DMA start and interrupt mask */
 815         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 816                       SD_CTL_DMA_START | SD_INT_MASK);
 817 }
 818
 819 /* stop a stream */
 820 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 821 {
 822         /* stop DMA */
 823         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 824                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 825         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 826         /* disable SIE */
 827         azx_writeb(chip, INTCTL,
 828                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 829 }
 830
 831
 832 /*
 833  * reset and start the controller registers
 834  */
 835 static void azx_init_chip(struct azx *chip)
 836 {
 837         if (chip->initialized)
 838                 return;
 839
 840         /* reset controller */
 841         azx_reset(chip);
 842
 843         /* initialize interrupts */
 844         azx_int_clear(chip);
 845         azx_int_enable(chip);
 846
 847         /* initialize the codec command I/O */
 848         if (!chip->single_cmd)
 849                 azx_init_cmd_io(chip);
 850
 851         /* program the position buffer */
 852         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 853         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 854
 855         chip->initialized = 1;
 856 }
 857
 858 /*
 859  * initialize the PCI registers
 860  */
 861 /* update bits in a PCI register byte */
 862 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 863                             unsigned char mask, unsigned char val)
 864 {
 865         unsigned char data;
 866
 867         pci_read_config_byte(pci, reg, &data);
 868         data &= ~mask;
 869         data |= (val & mask);
 870         pci_write_config_byte(pci, reg, data);
 871 }
 872
 873 static void azx_init_pci(struct azx *chip)
 874 {
 875         unsigned short snoop;
 876
 877         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 878          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 879          * Ensuring these bits are 0 clears playback static on some HD Audio
 880          * codecs
 881          */
 882         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 883
 884         switch (chip->driver_type) {
 885         case AZX_DRIVER_ATI:
 886                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 887                 update_pci_byte(chip->pci,
 888                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 889                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 890                 break;
 891         case AZX_DRIVER_NVIDIA:
 892                 /* For NVIDIA HDA, enable snoop */
 893                 update_pci_byte(chip->pci,
 894                                 NVIDIA_HDA_TRANSREG_ADDR,
 895                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 896                 break;
 897         case AZX_DRIVER_SCH:
 898                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 899                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 900                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 901                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 902                         pci_read_config_word(chip->pci,
 903                                 INTEL_SCH_HDA_DEVC, &snoop);
 904                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 905                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 906                                 ? "Failed" : "OK");
 907                 }
 908                 break;
 909
 910         }
 911 }
 912
 913
 914 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 915
 916 /*
 917  * interrupt handler
 918  */
 919 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 920 {
 921         struct azx *chip = dev_id;
 922         struct azx_dev *azx_dev;
 923         u32 status;
 924         int i;
 925
 926         spin_lock(&chip->reg_lock);
 927
 928         status = azx_readl(chip, INTSTS);
 929         if (status == 0) {
 930                 spin_unlock(&chip->reg_lock);
 931                 return IRQ_NONE;
 932         }
 933
 934         for (i = 0; i < chip->num_streams; i++) {
 935                 azx_dev = &chip->azx_dev[i];
 936                 if (status & azx_dev->sd_int_sta_mask) {
 937                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 938                         if (!azx_dev->substream || !azx_dev->running)
 939                                 continue;
 940                         /* check whether this IRQ is really acceptable */
 941                         if (azx_position_ok(chip, azx_dev)) {
 942                                 azx_dev->irq_pending = 0;
 943                                 spin_unlock(&chip->reg_lock);
 944                                 snd_pcm_period_elapsed(azx_dev->substream);
 945                                 spin_lock(&chip->reg_lock);
 946                         } else {
 947                                 /* bogus IRQ, process it later */
 948                                 azx_dev->irq_pending = 1;
 949                                 schedule_work(&chip->irq_pending_work);
 950                         }
 951                 }
 952         }
 953
 954         /* clear rirb int */
 955         status = azx_readb(chip, RIRBSTS);
 956         if (status & RIRB_INT_MASK) {
 957                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 958                         azx_update_rirb(chip);
 959                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 960         }
 961
 962 #if 0
 963         /* clear state status int */
 964         if (azx_readb(chip, STATESTS) & 0x04)
 965                 azx_writeb(chip, STATESTS, 0x04);
 966 #endif
 967         spin_unlock(&chip->reg_lock);
 968
 969         return IRQ_HANDLED;
 970 }
 971
 972
 973 /*
 974  * set up BDL entries
 975  */
 976 static int azx_setup_periods(struct snd_pcm_substream *substream,
 977                              struct azx_dev *azx_dev)
 978 {
 979         struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
 980         u32 *bdl;
 981         int i, ofs, periods, period_bytes;
 982
 983         /* reset BDL address */
 984         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 985         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 986
 987         period_bytes = snd_pcm_lib_period_bytes(substream);
 988         azx_dev->period_bytes = period_bytes;
 989         periods = azx_dev->bufsize / period_bytes;
 990
 991         /* program the initial BDL entries */
 992         bdl = (u32 *)azx_dev->bdl.area;
 993         ofs = 0;
 994         azx_dev->frags = 0;
 995         for (i = 0; i < periods; i++) {
 996                 int size, rest;
 997                 if (i >= AZX_MAX_BDL_ENTRIES) {
 998                         snd_printk(KERN_ERR "Too many BDL entries: "
 999                                    "buffer=%d, period=%d\n",
1000                                    azx_dev->bufsize, period_bytes);
1001                         /* reset */
1002                         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1003                         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1004                         return -EINVAL;
1005                 }
1006                 rest = period_bytes;
1007                 do {
1008                         dma_addr_t addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1009                         /* program the address field of the BDL entry */
1010                         bdl[0] = cpu_to_le32((u32)addr);
1011                         bdl[1] = cpu_to_le32(upper_32bit(addr));
1012                         /* program the size field of the BDL entry */
1013                         size = PAGE_SIZE - (ofs % PAGE_SIZE);
1014                         if (rest < size)
1015                                 size = rest;
1016                         bdl[2] = cpu_to_le32(size);
1017                         /* program the IOC to enable interrupt
1018                          * only when the whole fragment is processed
1019                          */
1020                         rest -= size;
1021                         bdl[3] = rest ? 0 : cpu_to_le32(0x01);
1022                         bdl += 4;
1023                         azx_dev->frags++;
1024                         ofs += size;
1025                 } while (rest > 0);
1026         }
1027         return 0;
1028 }
1029
1030 /*
1031  * set up the SD for streaming
1032  */
1033 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1034 {
1035         unsigned char val;
1036         int timeout;
1037
1038         /* make sure the run bit is zero for SD */
1039         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1040                       ~SD_CTL_DMA_START);
1041         /* reset stream */
1042         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1043                       SD_CTL_STREAM_RESET);
1044         udelay(3);
1045         timeout = 300;
1046         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1047                --timeout)
1048                 ;
1049         val &= ~SD_CTL_STREAM_RESET;
1050         azx_sd_writeb(azx_dev, SD_CTL, val);
1051         udelay(3);
1052
1053         timeout = 300;
1054         /* waiting for hardware to report that the stream is out of reset */
1055         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1056                --timeout)
1057                 ;
1058
1059         /* program the stream_tag */
1060         azx_sd_writel(azx_dev, SD_CTL,
1061                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1062                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1063
1064         /* program the length of samples in cyclic buffer */
1065         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1066
1067         /* program the stream format */
1068         /* this value needs to be the same as the one programmed */
1069         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1070
1071         /* program the stream LVI (last valid index) of the BDL */
1072         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1073
1074         /* program the BDL address */
1075         /* lower BDL address */
1076         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1077         /* upper BDL address */
1078         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1079
1080         /* enable the position buffer */
1081         if (chip->position_fix == POS_FIX_POSBUF ||
1082             chip->position_fix == POS_FIX_AUTO) {
1083                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1084                         azx_writel(chip, DPLBASE,
1085                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1086         }
1087
1088         /* set the interrupt enable bits in the descriptor control register */
1089         azx_sd_writel(azx_dev, SD_CTL,
1090                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1091
1092         return 0;
1093 }
1094
1095
1096 /*
1097  * Codec initialization
1098  */
1099
1100 static unsigned int azx_max_codecs[] __devinitdata = {
1101         [AZX_DRIVER_ICH] = 3,
1102         [AZX_DRIVER_SCH] = 3,
1103         [AZX_DRIVER_ATI] = 4,
1104         [AZX_DRIVER_ATIHDMI] = 4,
1105         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1106         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1107         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1108         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1109 };
1110
1111 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1112                                       unsigned int codec_probe_mask)
1113 {
1114         struct hda_bus_template bus_temp;
1115         int c, codecs, audio_codecs, err;
1116
1117         memset(&bus_temp, 0, sizeof(bus_temp));
1118         bus_temp.private_data = chip;
1119         bus_temp.modelname = model;
1120         bus_temp.pci = chip->pci;
1121         bus_temp.ops.command = azx_send_cmd;
1122         bus_temp.ops.get_response = azx_get_response;
1123 #ifdef CONFIG_SND_HDA_POWER_SAVE
1124         bus_temp.ops.pm_notify = azx_power_notify;
1125 #endif
1126
1127         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1128         if (err < 0)
1129                 return err;
1130
1131         codecs = audio_codecs = 0;
1132         for (c = 0; c < AZX_MAX_CODECS; c++) {
1133                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1134                         struct hda_codec *codec;
1135                         err = snd_hda_codec_new(chip->bus, c, &codec);
1136                         if (err < 0)
1137                                 continue;
1138                         codecs++;
1139                         if (codec->afg)
1140                                 audio_codecs++;
1141                 }
1142         }
1143         if (!audio_codecs) {
1144                 /* probe additional slots if no codec is found */
1145                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1146                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1147                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1148                                 if (err < 0)
1149                                         continue;
1150                                 codecs++;
1151                         }
1152                 }
1153         }
1154         if (!codecs) {
1155                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1156                 return -ENXIO;
1157         }
1158
1159         return 0;
1160 }
1161
1162
1163 /*
1164  * PCM support
1165  */
1166
1167 /* assign a stream for the PCM */
1168 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1169 {
1170         int dev, i, nums;
1171         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1172                 dev = chip->playback_index_offset;
1173                 nums = chip->playback_streams;
1174         } else {
1175                 dev = chip->capture_index_offset;
1176                 nums = chip->capture_streams;
1177         }
1178         for (i = 0; i < nums; i++, dev++)
1179                 if (!chip->azx_dev[dev].opened) {
1180                         chip->azx_dev[dev].opened = 1;
1181                         return &chip->azx_dev[dev];
1182                 }
1183         return NULL;
1184 }
1185
1186 /* release the assigned stream */
1187 static inline void azx_release_device(struct azx_dev *azx_dev)
1188 {
1189         azx_dev->opened = 0;
1190 }
1191
1192 static struct snd_pcm_hardware azx_pcm_hw = {
1193         .info =                 (SNDRV_PCM_INFO_MMAP |
1194                                  SNDRV_PCM_INFO_INTERLEAVED |
1195                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1196                                  SNDRV_PCM_INFO_MMAP_VALID |
1197                                  /* No full-resume yet implemented */
1198                                  /* SNDRV_PCM_INFO_RESUME |*/
1199                                  SNDRV_PCM_INFO_PAUSE |
1200                                  SNDRV_PCM_INFO_SYNC_START),
1201         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1202         .rates =                SNDRV_PCM_RATE_48000,
1203         .rate_min =             48000,
1204         .rate_max =             48000,
1205         .channels_min =         2,
1206         .channels_max =         2,
1207         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1208         .period_bytes_min =     128,
1209         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1210         .periods_min =          2,
1211         .periods_max =          AZX_MAX_FRAG,
1212         .fifo_size =            0,
1213 };
1214
1215 struct azx_pcm {
1216         struct azx *chip;
1217         struct hda_codec *codec;
1218         struct hda_pcm_stream *hinfo[2];
1219 };
1220
1221 static int azx_pcm_open(struct snd_pcm_substream *substream)
1222 {
1223         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1224         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1225         struct azx *chip = apcm->chip;
1226         struct azx_dev *azx_dev;
1227         struct snd_pcm_runtime *runtime = substream->runtime;
1228         unsigned long flags;
1229         int err;
1230
1231         mutex_lock(&chip->open_mutex);
1232         azx_dev = azx_assign_device(chip, substream->stream);
1233         if (azx_dev == NULL) {
1234                 mutex_unlock(&chip->open_mutex);
1235                 return -EBUSY;
1236         }
1237         runtime->hw = azx_pcm_hw;
1238         runtime->hw.channels_min = hinfo->channels_min;
1239         runtime->hw.channels_max = hinfo->channels_max;
1240         runtime->hw.formats = hinfo->formats;
1241         runtime->hw.rates = hinfo->rates;
1242         snd_pcm_limit_hw_rates(runtime);
1243         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1244         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1245                                    128);
1246         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1247                                    128);
1248         snd_hda_power_up(apcm->codec);
1249         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1250         if (err < 0) {
1251                 azx_release_device(azx_dev);
1252                 snd_hda_power_down(apcm->codec);
1253                 mutex_unlock(&chip->open_mutex);
1254                 return err;
1255         }
1256         spin_lock_irqsave(&chip->reg_lock, flags);
1257         azx_dev->substream = substream;
1258         azx_dev->running = 0;
1259         spin_unlock_irqrestore(&chip->reg_lock, flags);
1260
1261         runtime->private_data = azx_dev;
1262         snd_pcm_set_sync(substream);
1263         mutex_unlock(&chip->open_mutex);
1264         return 0;
1265 }
1266
1267 static int azx_pcm_close(struct snd_pcm_substream *substream)
1268 {
1269         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1270         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1271         struct azx *chip = apcm->chip;
1272         struct azx_dev *azx_dev = get_azx_dev(substream);
1273         unsigned long flags;
1274
1275         mutex_lock(&chip->open_mutex);
1276         spin_lock_irqsave(&chip->reg_lock, flags);
1277         azx_dev->substream = NULL;
1278         azx_dev->running = 0;
1279         spin_unlock_irqrestore(&chip->reg_lock, flags);
1280         azx_release_device(azx_dev);
1281         hinfo->ops.close(hinfo, apcm->codec, substream);
1282         snd_hda_power_down(apcm->codec);
1283         mutex_unlock(&chip->open_mutex);
1284         return 0;
1285 }
1286
1287 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1288                              struct snd_pcm_hw_params *hw_params)
1289 {
1290         return snd_pcm_lib_malloc_pages(substream,
1291                                         params_buffer_bytes(hw_params));
1292 }
1293
1294 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1295 {
1296         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1297         struct azx_dev *azx_dev = get_azx_dev(substream);
1298         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1299
1300         /* reset BDL address */
1301         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1302         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1303         azx_sd_writel(azx_dev, SD_CTL, 0);
1304
1305         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1306
1307         return snd_pcm_lib_free_pages(substream);
1308 }
1309
1310 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1311 {
1312         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1313         struct azx *chip = apcm->chip;
1314         struct azx_dev *azx_dev = get_azx_dev(substream);
1315         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1316         struct snd_pcm_runtime *runtime = substream->runtime;
1317
1318         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1319         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1320                                                          runtime->channels,
1321                                                          runtime->format,
1322                                                          hinfo->maxbps);
1323         if (!azx_dev->format_val) {
1324                 snd_printk(KERN_ERR SFX
1325                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1326                            runtime->rate, runtime->channels, runtime->format);
1327                 return -EINVAL;
1328         }
1329
1330         snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1331                     azx_dev->bufsize, azx_dev->format_val);
1332         if (azx_setup_periods(substream, azx_dev) < 0)
1333                 return -EINVAL;
1334         azx_setup_controller(chip, azx_dev);
1335         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1336                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1337         else
1338                 azx_dev->fifo_size = 0;
1339
1340         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1341                                   azx_dev->format_val, substream);
1342 }
1343
1344 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1345 {
1346         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1347         struct azx *chip = apcm->chip;
1348         struct azx_dev *azx_dev;
1349         struct snd_pcm_substream *s;
1350         int start, nsync = 0, sbits = 0;
1351         int nwait, timeout;
1352
1353         switch (cmd) {
1354         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1355         case SNDRV_PCM_TRIGGER_RESUME:
1356         case SNDRV_PCM_TRIGGER_START:
1357                 start = 1;
1358                 break;
1359         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1360         case SNDRV_PCM_TRIGGER_SUSPEND:
1361         case SNDRV_PCM_TRIGGER_STOP:
1362                 start = 0;
1363                 break;
1364         default:
1365                 return -EINVAL;
1366         }
1367
1368         snd_pcm_group_for_each_entry(s, substream) {
1369                 if (s->pcm->card != substream->pcm->card)
1370                         continue;
1371                 azx_dev = get_azx_dev(s);
1372                 sbits |= 1 << azx_dev->index;
1373                 nsync++;
1374                 snd_pcm_trigger_done(s, substream);
1375         }
1376
1377         spin_lock(&chip->reg_lock);
1378         if (nsync > 1) {
1379                 /* first, set SYNC bits of corresponding streams */
1380                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1381         }
1382         snd_pcm_group_for_each_entry(s, substream) {
1383                 if (s->pcm->card != substream->pcm->card)
1384                         continue;
1385                 azx_dev = get_azx_dev(s);
1386                 if (start)
1387                         azx_stream_start(chip, azx_dev);
1388                 else
1389                         azx_stream_stop(chip, azx_dev);
1390                 azx_dev->running = start;
1391         }
1392         spin_unlock(&chip->reg_lock);
1393         if (start) {
1394                 if (nsync == 1)
1395                         return 0;
1396                 /* wait until all FIFOs get ready */
1397                 for (timeout = 5000; timeout; timeout--) {
1398                         nwait = 0;
1399                         snd_pcm_group_for_each_entry(s, substream) {
1400                                 if (s->pcm->card != substream->pcm->card)
1401                                         continue;
1402                                 azx_dev = get_azx_dev(s);
1403                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1404                                       SD_STS_FIFO_READY))
1405                                         nwait++;
1406                         }
1407                         if (!nwait)
1408                                 break;
1409                         cpu_relax();
1410                 }
1411         } else {
1412                 /* wait until all RUN bits are cleared */
1413                 for (timeout = 5000; timeout; timeout--) {
1414                         nwait = 0;
1415                         snd_pcm_group_for_each_entry(s, substream) {
1416                                 if (s->pcm->card != substream->pcm->card)
1417                                         continue;
1418                                 azx_dev = get_azx_dev(s);
1419                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1420                                     SD_CTL_DMA_START)
1421                                         nwait++;
1422                         }
1423                         if (!nwait)
1424                                 break;
1425                         cpu_relax();
1426                 }
1427         }
1428         if (nsync > 1) {
1429                 spin_lock(&chip->reg_lock);
1430                 /* reset SYNC bits */
1431                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1432                 spin_unlock(&chip->reg_lock);
1433         }
1434         return 0;
1435 }
1436
1437 static unsigned int azx_get_position(struct azx *chip,
1438                                      struct azx_dev *azx_dev)
1439 {
1440         unsigned int pos;
1441
1442         if (chip->position_fix == POS_FIX_POSBUF ||
1443             chip->position_fix == POS_FIX_AUTO) {
1444                 /* use the position buffer */
1445                 pos = le32_to_cpu(*azx_dev->posbuf);
1446         } else {
1447                 /* read LPIB */
1448                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1449                 if (chip->position_fix == POS_FIX_FIFO)
1450                         pos += azx_dev->fifo_size;
1451         }
1452         if (pos >= azx_dev->bufsize)
1453                 pos = 0;
1454         return pos;
1455 }
1456
1457 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1458 {
1459         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1460         struct azx *chip = apcm->chip;
1461         struct azx_dev *azx_dev = get_azx_dev(substream);
1462         return bytes_to_frames(substream->runtime,
1463                                azx_get_position(chip, azx_dev));
1464 }
1465
1466 /*
1467  * Check whether the current DMA position is acceptable for updating
1468  * periods.  Returns non-zero if it's OK.
1469  *
1470  * Many HD-audio controllers appear pretty inaccurate about
1471  * the update-IRQ timing.  The IRQ is issued before actually the
1472  * data is processed.  So, we need to process it afterwords in a
1473  * workqueue.
1474  */
1475 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1476 {
1477         unsigned int pos;
1478
1479         pos = azx_get_position(chip, azx_dev);
1480         if (chip->position_fix == POS_FIX_AUTO) {
1481                 if (!pos) {
1482                         printk(KERN_WARNING
1483                                "hda-intel: Invalid position buffer, "
1484                                "using LPIB read method instead.\n");
1485                         chip->position_fix = POS_FIX_NONE;
1486                         pos = azx_get_position(chip, azx_dev);
1487                 } else
1488                         chip->position_fix = POS_FIX_POSBUF;
1489         }
1490
1491         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1492                 return 0; /* NG - it's below the period boundary */
1493         return 1; /* OK, it's fine */
1494 }
1495
1496 /*
1497  * The work for pending PCM period updates.
1498  */
1499 static void azx_irq_pending_work(struct work_struct *work)
1500 {
1501         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1502         int i, pending;
1503
1504         for (;;) {
1505                 pending = 0;
1506                 spin_lock_irq(&chip->reg_lock);
1507                 for (i = 0; i < chip->num_streams; i++) {
1508                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1509                         if (!azx_dev->irq_pending ||
1510                             !azx_dev->substream ||
1511                             !azx_dev->running)
1512                                 continue;
1513                         if (azx_position_ok(chip, azx_dev)) {
1514                                 azx_dev->irq_pending = 0;
1515                                 spin_unlock(&chip->reg_lock);
1516                                 snd_pcm_period_elapsed(azx_dev->substream);
1517                                 spin_lock(&chip->reg_lock);
1518                         } else
1519                                 pending++;
1520                 }
1521                 spin_unlock_irq(&chip->reg_lock);
1522                 if (!pending)
1523                         return;
1524                 cond_resched();
1525         }
1526 }
1527
1528 /* clear irq_pending flags and assure no on-going workq */
1529 static void azx_clear_irq_pending(struct azx *chip)
1530 {
1531         int i;
1532
1533         spin_lock_irq(&chip->reg_lock);
1534         for (i = 0; i < chip->num_streams; i++)
1535                 chip->azx_dev[i].irq_pending = 0;
1536         spin_unlock_irq(&chip->reg_lock);
1537         flush_scheduled_work();
1538 }
1539
1540 static struct snd_pcm_ops azx_pcm_ops = {
1541         .open = azx_pcm_open,
1542         .close = azx_pcm_close,
1543         .ioctl = snd_pcm_lib_ioctl,
1544         .hw_params = azx_pcm_hw_params,
1545         .hw_free = azx_pcm_hw_free,
1546         .prepare = azx_pcm_prepare,
1547         .trigger = azx_pcm_trigger,
1548         .pointer = azx_pcm_pointer,
1549         .page = snd_pcm_sgbuf_ops_page,
1550 };
1551
1552 static void azx_pcm_free(struct snd_pcm *pcm)
1553 {
1554         kfree(pcm->private_data);
1555 }
1556
1557 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1558                                       struct hda_pcm *cpcm)
1559 {
1560         int err;
1561         struct snd_pcm *pcm;
1562         struct azx_pcm *apcm;
1563
1564         /* if no substreams are defined for both playback and capture,
1565          * it's just a placeholder.  ignore it.
1566          */
1567         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1568                 return 0;
1569
1570         snd_assert(cpcm->name, return -EINVAL);
1571
1572         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1573                           cpcm->stream[0].substreams,
1574                           cpcm->stream[1].substreams,
1575                           &pcm);
1576         if (err < 0)
1577                 return err;
1578         strcpy(pcm->name, cpcm->name);
1579         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1580         if (apcm == NULL)
1581                 return -ENOMEM;
1582         apcm->chip = chip;
1583         apcm->codec = codec;
1584         apcm->hinfo[0] = &cpcm->stream[0];
1585         apcm->hinfo[1] = &cpcm->stream[1];
1586         pcm->private_data = apcm;
1587         pcm->private_free = azx_pcm_free;
1588         if (cpcm->stream[0].substreams)
1589                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1590         if (cpcm->stream[1].substreams)
1591                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1592         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1593                                               snd_dma_pci_data(chip->pci),
1594                                               1024 * 64, 1024 * 1024);
1595         chip->pcm[cpcm->device] = pcm;
1596         return 0;
1597 }
1598
1599 static int __devinit azx_pcm_create(struct azx *chip)
1600 {
1601         static const char *dev_name[HDA_PCM_NTYPES] = {
1602                 "Audio", "SPDIF", "HDMI", "Modem"
1603         };
1604         /* starting device index for each PCM type */
1605         static int dev_idx[HDA_PCM_NTYPES] = {
1606                 [HDA_PCM_TYPE_AUDIO] = 0,
1607                 [HDA_PCM_TYPE_SPDIF] = 1,
1608                 [HDA_PCM_TYPE_HDMI] = 3,
1609                 [HDA_PCM_TYPE_MODEM] = 6
1610         };
1611         /* normal audio device indices; not linear to keep compatibility */
1612         static int audio_idx[4] = { 0, 2, 4, 5 };
1613         struct hda_codec *codec;
1614         int c, err;
1615         int num_devs[HDA_PCM_NTYPES];
1616
1617         err = snd_hda_build_pcms(chip->bus);
1618         if (err < 0)
1619                 return err;
1620
1621         /* create audio PCMs */
1622         memset(num_devs, 0, sizeof(num_devs));
1623         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1624                 for (c = 0; c < codec->num_pcms; c++) {
1625                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1626                         int type = cpcm->pcm_type;
1627                         switch (type) {
1628                         case HDA_PCM_TYPE_AUDIO:
1629                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1630                                         snd_printk(KERN_WARNING
1631                                                    "Too many audio devices\n");
1632                                         continue;
1633                                 }
1634                                 cpcm->device = audio_idx[num_devs[type]];
1635                                 break;
1636                         case HDA_PCM_TYPE_SPDIF:
1637                         case HDA_PCM_TYPE_HDMI:
1638                         case HDA_PCM_TYPE_MODEM:
1639                                 if (num_devs[type]) {
1640                                         snd_printk(KERN_WARNING
1641                                                    "%s already defined\n",
1642                                                    dev_name[type]);
1643                                         continue;
1644                                 }
1645                                 cpcm->device = dev_idx[type];
1646                                 break;
1647                         default:
1648                                 snd_printk(KERN_WARNING
1649                                            "Invalid PCM type %d\n", type);
1650                                 continue;
1651                         }
1652                         num_devs[type]++;
1653                         err = create_codec_pcm(chip, codec, cpcm);
1654                         if (err < 0)
1655                                 return err;
1656                 }
1657         }
1658         return 0;
1659 }
1660
1661 /*
1662  * mixer creation - all stuff is implemented in hda module
1663  */
1664 static int __devinit azx_mixer_create(struct azx *chip)
1665 {
1666         return snd_hda_build_controls(chip->bus);
1667 }
1668
1669
1670 /*
1671  * initialize SD streams
1672  */
1673 static int __devinit azx_init_stream(struct azx *chip)
1674 {
1675         int i;
1676
1677         /* initialize each stream (aka device)
1678          * assign the starting bdl address to each stream (device)
1679          * and initialize
1680          */
1681         for (i = 0; i < chip->num_streams; i++) {
1682                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1683                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1684                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1685                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1686                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1687                 azx_dev->sd_int_sta_mask = 1 << i;
1688                 /* stream tag: must be non-zero and unique */
1689                 azx_dev->index = i;
1690                 azx_dev->stream_tag = i + 1;
1691         }
1692
1693         return 0;
1694 }
1695
1696 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1697 {
1698         if (request_irq(chip->pci->irq, azx_interrupt,
1699                         chip->msi ? 0 : IRQF_SHARED,
1700                         "HDA Intel", chip)) {
1701                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1702                        "disabling device\n", chip->pci->irq);
1703                 if (do_disconnect)
1704                         snd_card_disconnect(chip->card);
1705                 return -1;
1706         }
1707         chip->irq = chip->pci->irq;
1708         pci_intx(chip->pci, !chip->msi);
1709         return 0;
1710 }
1711
1712
1713 static void azx_stop_chip(struct azx *chip)
1714 {
1715         if (!chip->initialized)
1716                 return;
1717
1718         /* disable interrupts */
1719         azx_int_disable(chip);
1720         azx_int_clear(chip);
1721
1722         /* disable CORB/RIRB */
1723         azx_free_cmd_io(chip);
1724
1725         /* disable position buffer */
1726         azx_writel(chip, DPLBASE, 0);
1727         azx_writel(chip, DPUBASE, 0);
1728
1729         chip->initialized = 0;
1730 }
1731
1732 #ifdef CONFIG_SND_HDA_POWER_SAVE
1733 /* power-up/down the controller */
1734 static void azx_power_notify(struct hda_codec *codec)
1735 {
1736         struct azx *chip = codec->bus->private_data;
1737         struct hda_codec *c;
1738         int power_on = 0;
1739
1740         list_for_each_entry(c, &codec->bus->codec_list, list) {
1741                 if (c->power_on) {
1742                         power_on = 1;
1743                         break;
1744                 }
1745         }
1746         if (power_on)
1747                 azx_init_chip(chip);
1748         else if (chip->running && power_save_controller)
1749                 azx_stop_chip(chip);
1750 }
1751 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1752
1753 #ifdef CONFIG_PM
1754 /*
1755  * power management
1756  */
1757 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1758 {
1759         struct snd_card *card = pci_get_drvdata(pci);
1760         struct azx *chip = card->private_data;
1761         int i;
1762
1763         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1764         azx_clear_irq_pending(chip);
1765         for (i = 0; i < AZX_MAX_PCMS; i++)
1766                 snd_pcm_suspend_all(chip->pcm[i]);
1767         if (chip->initialized)
1768                 snd_hda_suspend(chip->bus, state);
1769         azx_stop_chip(chip);
1770         if (chip->irq >= 0) {
1771                 free_irq(chip->irq, chip);
1772                 chip->irq = -1;
1773         }
1774         if (chip->msi)
1775                 pci_disable_msi(chip->pci);
1776         pci_disable_device(pci);
1777         pci_save_state(pci);
1778         pci_set_power_state(pci, pci_choose_state(pci, state));
1779         return 0;
1780 }
1781
1782 static int azx_resume(struct pci_dev *pci)
1783 {
1784         struct snd_card *card = pci_get_drvdata(pci);
1785         struct azx *chip = card->private_data;
1786
1787         pci_set_power_state(pci, PCI_D0);
1788         pci_restore_state(pci);
1789         if (pci_enable_device(pci) < 0) {
1790                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1791                        "disabling device\n");
1792                 snd_card_disconnect(card);
1793                 return -EIO;
1794         }
1795         pci_set_master(pci);
1796         if (chip->msi)
1797                 if (pci_enable_msi(pci) < 0)
1798                         chip->msi = 0;
1799         if (azx_acquire_irq(chip, 1) < 0)
1800                 return -EIO;
1801         azx_init_pci(chip);
1802
1803         if (snd_hda_codecs_inuse(chip->bus))
1804                 azx_init_chip(chip);
1805
1806         snd_hda_resume(chip->bus);
1807         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1808         return 0;
1809 }
1810 #endif /* CONFIG_PM */
1811
1812
1813 /*
1814  * destructor
1815  */
1816 static int azx_free(struct azx *chip)
1817 {
1818         int i;
1819
1820         if (chip->initialized) {
1821                 azx_clear_irq_pending(chip);
1822                 for (i = 0; i < chip->num_streams; i++)
1823                         azx_stream_stop(chip, &chip->azx_dev[i]);
1824                 azx_stop_chip(chip);
1825         }
1826
1827         if (chip->irq >= 0)
1828                 free_irq(chip->irq, (void*)chip);
1829         if (chip->msi)
1830                 pci_disable_msi(chip->pci);
1831         if (chip->remap_addr)
1832                 iounmap(chip->remap_addr);
1833
1834         if (chip->azx_dev) {
1835                 for (i = 0; i < chip->num_streams; i++)
1836                         if (chip->azx_dev[i].bdl.area)
1837                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1838         }
1839         if (chip->rb.area)
1840                 snd_dma_free_pages(&chip->rb);
1841         if (chip->posbuf.area)
1842                 snd_dma_free_pages(&chip->posbuf);
1843         pci_release_regions(chip->pci);
1844         pci_disable_device(chip->pci);
1845         kfree(chip->azx_dev);
1846         kfree(chip);
1847
1848         return 0;
1849 }
1850
1851 static int azx_dev_free(struct snd_device *device)
1852 {
1853         return azx_free(device->device_data);
1854 }
1855
1856 /*
1857  * white/black-listing for position_fix
1858  */
1859 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1860         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1861         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1862         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_NONE),
1863         {}
1864 };
1865
1866 static int __devinit check_position_fix(struct azx *chip, int fix)
1867 {
1868         const struct snd_pci_quirk *q;
1869
1870         if (fix == POS_FIX_AUTO) {
1871                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1872                 if (q) {
1873                         printk(KERN_INFO
1874                                     "hda_intel: position_fix set to %d "
1875                                     "for device %04x:%04x\n",
1876                                     q->value, q->subvendor, q->subdevice);
1877                         return q->value;
1878                 }
1879         }
1880         return fix;
1881 }
1882
1883 /*
1884  * black-lists for probe_mask
1885  */
1886 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1887         /* Thinkpad often breaks the controller communication when accessing
1888          * to the non-working (or non-existing) modem codec slot.
1889          */
1890         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1891         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1892         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1893         {}
1894 };
1895
1896 static void __devinit check_probe_mask(struct azx *chip, int dev)
1897 {
1898         const struct snd_pci_quirk *q;
1899
1900         if (probe_mask[dev] == -1) {
1901                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1902                 if (q) {
1903                         printk(KERN_INFO
1904                                "hda_intel: probe_mask set to 0x%x "
1905                                "for device %04x:%04x\n",
1906                                q->value, q->subvendor, q->subdevice);
1907                         probe_mask[dev] = q->value;
1908                 }
1909         }
1910 }
1911
1912
1913 /*
1914  * constructor
1915  */
1916 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1917                                 int dev, int driver_type,
1918                                 struct azx **rchip)
1919 {
1920         struct azx *chip;
1921         int i, err;
1922         unsigned short gcap;
1923         static struct snd_device_ops ops = {
1924                 .dev_free = azx_dev_free,
1925         };
1926
1927         *rchip = NULL;
1928
1929         err = pci_enable_device(pci);
1930         if (err < 0)
1931                 return err;
1932
1933         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1934         if (!chip) {
1935                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1936                 pci_disable_device(pci);
1937                 return -ENOMEM;
1938         }
1939
1940         spin_lock_init(&chip->reg_lock);
1941         mutex_init(&chip->open_mutex);
1942         chip->card = card;
1943         chip->pci = pci;
1944         chip->irq = -1;
1945         chip->driver_type = driver_type;
1946         chip->msi = enable_msi;
1947         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1948
1949         chip->position_fix = check_position_fix(chip, position_fix[dev]);
1950         check_probe_mask(chip, dev);
1951
1952         chip->single_cmd = single_cmd;
1953
1954 #if BITS_PER_LONG != 64
1955         /* Fix up base address on ULI M5461 */
1956         if (chip->driver_type == AZX_DRIVER_ULI) {
1957                 u16 tmp3;
1958                 pci_read_config_word(pci, 0x40, &tmp3);
1959                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1960                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1961         }
1962 #endif
1963
1964         err = pci_request_regions(pci, "ICH HD audio");
1965         if (err < 0) {
1966                 kfree(chip);
1967                 pci_disable_device(pci);
1968                 return err;
1969         }
1970
1971         chip->addr = pci_resource_start(pci, 0);
1972         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1973         if (chip->remap_addr == NULL) {
1974                 snd_printk(KERN_ERR SFX "ioremap error\n");
1975                 err = -ENXIO;
1976                 goto errout;
1977         }
1978
1979         if (chip->msi)
1980                 if (pci_enable_msi(pci) < 0)
1981                         chip->msi = 0;
1982
1983         if (azx_acquire_irq(chip, 0) < 0) {
1984                 err = -EBUSY;
1985                 goto errout;
1986         }
1987
1988         pci_set_master(pci);
1989         synchronize_irq(chip->irq);
1990
1991         gcap = azx_readw(chip, GCAP);
1992         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1993
1994         /* allow 64bit DMA address if supported by H/W */
1995         if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
1996                 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
1997
1998         /* read number of streams from GCAP register instead of using
1999          * hardcoded value
2000          */
2001         chip->capture_streams = (gcap >> 8) & 0x0f;
2002         chip->playback_streams = (gcap >> 12) & 0x0f;
2003         if (!chip->playback_streams && !chip->capture_streams) {
2004                 /* gcap didn't give any info, switching to old method */
2005
2006                 switch (chip->driver_type) {
2007                 case AZX_DRIVER_ULI:
2008                         chip->playback_streams = ULI_NUM_PLAYBACK;
2009                         chip->capture_streams = ULI_NUM_CAPTURE;
2010                         break;
2011                 case AZX_DRIVER_ATIHDMI:
2012                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2013                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2014                         break;
2015                 default:
2016                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2017                         chip->capture_streams = ICH6_NUM_CAPTURE;
2018                         break;
2019                 }
2020         }
2021         chip->capture_index_offset = 0;
2022         chip->playback_index_offset = chip->capture_streams;
2023         chip->num_streams = chip->playback_streams + chip->capture_streams;
2024         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2025                                 GFP_KERNEL);
2026         if (!chip->azx_dev) {
2027                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2028                 goto errout;
2029         }
2030
2031         for (i = 0; i < chip->num_streams; i++) {
2032                 /* allocate memory for the BDL for each stream */
2033                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2034                                           snd_dma_pci_data(chip->pci),
2035                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2036                 if (err < 0) {
2037                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2038                         goto errout;
2039                 }
2040         }
2041         /* allocate memory for the position buffer */
2042         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2043                                   snd_dma_pci_data(chip->pci),
2044                                   chip->num_streams * 8, &chip->posbuf);
2045         if (err < 0) {
2046                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2047                 goto errout;
2048         }
2049         /* allocate CORB/RIRB */
2050         if (!chip->single_cmd) {
2051                 err = azx_alloc_cmd_io(chip);
2052                 if (err < 0)
2053                         goto errout;
2054         }
2055
2056         /* initialize streams */
2057         azx_init_stream(chip);
2058
2059         /* initialize chip */
2060         azx_init_pci(chip);
2061         azx_init_chip(chip);
2062
2063         /* codec detection */
2064         if (!chip->codec_mask) {
2065                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2066                 err = -ENODEV;
2067                 goto errout;
2068         }
2069
2070         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2071         if (err <0) {
2072                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2073                 goto errout;
2074         }
2075
2076         strcpy(card->driver, "HDA-Intel");
2077         strcpy(card->shortname, driver_short_names[chip->driver_type]);
2078         sprintf(card->longname, "%s at 0x%lx irq %i",
2079                 card->shortname, chip->addr, chip->irq);
2080
2081         *rchip = chip;
2082         return 0;
2083
2084  errout:
2085         azx_free(chip);
2086         return err;
2087 }
2088
2089 static void power_down_all_codecs(struct azx *chip)
2090 {
2091 #ifdef CONFIG_SND_HDA_POWER_SAVE
2092         /* The codecs were powered up in snd_hda_codec_new().
2093          * Now all initialization done, so turn them down if possible
2094          */
2095         struct hda_codec *codec;
2096         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2097                 snd_hda_power_down(codec);
2098         }
2099 #endif
2100 }
2101
2102 static int __devinit azx_probe(struct pci_dev *pci,
2103                                const struct pci_device_id *pci_id)
2104 {
2105         static int dev;
2106         struct snd_card *card;
2107         struct azx *chip;
2108         int err;
2109
2110         if (dev >= SNDRV_CARDS)
2111                 return -ENODEV;
2112         if (!enable[dev]) {
2113                 dev++;
2114                 return -ENOENT;
2115         }
2116
2117         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2118         if (!card) {
2119                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2120                 return -ENOMEM;
2121         }
2122
2123         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2124         if (err < 0) {
2125                 snd_card_free(card);
2126                 return err;
2127         }
2128         card->private_data = chip;
2129
2130         /* create codec instances */
2131         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2132         if (err < 0) {
2133                 snd_card_free(card);
2134                 return err;
2135         }
2136
2137         /* create PCM streams */
2138         err = azx_pcm_create(chip);
2139         if (err < 0) {
2140                 snd_card_free(card);
2141                 return err;
2142         }
2143
2144         /* create mixer controls */
2145         err = azx_mixer_create(chip);
2146         if (err < 0) {
2147                 snd_card_free(card);
2148                 return err;
2149         }
2150
2151         snd_card_set_dev(card, &pci->dev);
2152
2153         err = snd_card_register(card);
2154         if (err < 0) {
2155                 snd_card_free(card);
2156                 return err;
2157         }
2158
2159         pci_set_drvdata(pci, card);
2160         chip->running = 1;
2161         power_down_all_codecs(chip);
2162
2163         dev++;
2164         return err;
2165 }
2166
2167 static void __devexit azx_remove(struct pci_dev *pci)
2168 {
2169         snd_card_free(pci_get_drvdata(pci));
2170         pci_set_drvdata(pci, NULL);
2171 }
2172
2173 /* PCI IDs */
2174 static struct pci_device_id azx_ids[] = {
2175         /* ICH 6..10 */
2176         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2177         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2178         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2179         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2180         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2181         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2182         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2183         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2184         /* SCH */
2185         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2186         /* ATI SB 450/600 */
2187         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2188         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2189         /* ATI HDMI */
2190         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2191         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2192         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2193         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2194         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2195         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2196         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2197         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2198         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2199         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2200         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2201         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2202         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2203         /* VIA VT8251/VT8237A */
2204         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2205         /* SIS966 */
2206         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2207         /* ULI M5461 */
2208         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2209         /* NVIDIA MCP */
2210         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2211         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2212         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2213         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2214         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2215         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2216         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2217         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2218         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2219         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2220         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2221         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2222         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2223         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2224         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2225         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2226         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2227         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2228         { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2229         { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2230         { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2231         { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2232         { 0, }
2233 };
2234 MODULE_DEVICE_TABLE(pci, azx_ids);
2235
2236 /* pci_driver definition */
2237 static struct pci_driver driver = {
2238         .name = "HDA Intel",
2239         .id_table = azx_ids,
2240         .probe = azx_probe,
2241         .remove = __devexit_p(azx_remove),
2242 #ifdef CONFIG_PM
2243         .suspend = azx_suspend,
2244         .resume = azx_resume,
2245 #endif
2246 };
2247
2248 static int __init alsa_card_azx_init(void)
2249 {
2250         return pci_register_driver(&driver);
2251 }
2252
2253 static void __exit alsa_card_azx_exit(void)
2254 {
2255         pci_unregister_driver(&driver);
2256 }
2257
2258 module_init(alsa_card_azx_init)
2259 module_exit(alsa_card_azx_exit)