3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int single_cmd;
61 static int enable_msi;
63 module_param_array(index, int, NULL, 0444);
64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
65 module_param_array(id, charp, NULL, 0444);
66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
67 module_param_array(enable, bool, NULL, 0444);
68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
69 module_param_array(model, charp, NULL, 0444);
70 MODULE_PARM_DESC(model, "Use the given board model.");
71 module_param_array(position_fix, int, NULL, 0444);
72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
73 "(0 = auto, 1 = none, 2 = POSBUF).");
74 module_param_array(bdl_pos_adj, int, NULL, 0644);
75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
76 module_param_array(probe_mask, int, NULL, 0444);
77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
78 module_param(single_cmd, bool, 0444);
79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
80 "(for debugging only).");
81 module_param(enable_msi, int, 0444);
82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
84 #ifdef CONFIG_SND_HDA_POWER_SAVE
85 /* power_save option is defined in hda_codec.c */
87 /* reset the HD-audio controller in power save mode.
88 * this may give more power-saving, but will take longer time to
91 static int power_save_controller = 1;
92 module_param(power_save_controller, bool, 0644);
93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
96 MODULE_LICENSE("GPL");
97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
121 MODULE_DESCRIPTION("Intel HDA driver");
123 #define SFX "hda-intel: "
129 #define ICH6_REG_GCAP 0x00
130 #define ICH6_REG_VMIN 0x02
131 #define ICH6_REG_VMAJ 0x03
132 #define ICH6_REG_OUTPAY 0x04
133 #define ICH6_REG_INPAY 0x06
134 #define ICH6_REG_GCTL 0x08
135 #define ICH6_REG_WAKEEN 0x0c
136 #define ICH6_REG_STATESTS 0x0e
137 #define ICH6_REG_GSTS 0x10
138 #define ICH6_REG_INTCTL 0x20
139 #define ICH6_REG_INTSTS 0x24
140 #define ICH6_REG_WALCLK 0x30
141 #define ICH6_REG_SYNC 0x34
142 #define ICH6_REG_CORBLBASE 0x40
143 #define ICH6_REG_CORBUBASE 0x44
144 #define ICH6_REG_CORBWP 0x48
145 #define ICH6_REG_CORBRP 0x4A
146 #define ICH6_REG_CORBCTL 0x4c
147 #define ICH6_REG_CORBSTS 0x4d
148 #define ICH6_REG_CORBSIZE 0x4e
150 #define ICH6_REG_RIRBLBASE 0x50
151 #define ICH6_REG_RIRBUBASE 0x54
152 #define ICH6_REG_RIRBWP 0x58
153 #define ICH6_REG_RINTCNT 0x5a
154 #define ICH6_REG_RIRBCTL 0x5c
155 #define ICH6_REG_RIRBSTS 0x5d
156 #define ICH6_REG_RIRBSIZE 0x5e
158 #define ICH6_REG_IC 0x60
159 #define ICH6_REG_IR 0x64
160 #define ICH6_REG_IRS 0x68
161 #define ICH6_IRS_VALID (1<<1)
162 #define ICH6_IRS_BUSY (1<<0)
164 #define ICH6_REG_DPLBASE 0x70
165 #define ICH6_REG_DPUBASE 0x74
166 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
168 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
169 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
171 /* stream register offsets from stream base */
172 #define ICH6_REG_SD_CTL 0x00
173 #define ICH6_REG_SD_STS 0x03
174 #define ICH6_REG_SD_LPIB 0x04
175 #define ICH6_REG_SD_CBL 0x08
176 #define ICH6_REG_SD_LVI 0x0c
177 #define ICH6_REG_SD_FIFOW 0x0e
178 #define ICH6_REG_SD_FIFOSIZE 0x10
179 #define ICH6_REG_SD_FORMAT 0x12
180 #define ICH6_REG_SD_BDLPL 0x18
181 #define ICH6_REG_SD_BDLPU 0x1c
184 #define ICH6_PCIREG_TCSEL 0x44
190 /* max number of SDs */
191 /* ICH, ATI and VIA have 4 playback and 4 capture */
192 #define ICH6_NUM_CAPTURE 4
193 #define ICH6_NUM_PLAYBACK 4
195 /* ULI has 6 playback and 5 capture */
196 #define ULI_NUM_CAPTURE 5
197 #define ULI_NUM_PLAYBACK 6
199 /* ATI HDMI has 1 playback and 0 capture */
200 #define ATIHDMI_NUM_CAPTURE 0
201 #define ATIHDMI_NUM_PLAYBACK 1
203 /* TERA has 4 playback and 3 capture */
204 #define TERA_NUM_CAPTURE 3
205 #define TERA_NUM_PLAYBACK 4
207 /* this number is statically defined for simplicity */
208 #define MAX_AZX_DEV 16
210 /* max number of fragments - we may use more if allocating more pages for BDL */
211 #define BDL_SIZE 4096
212 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
213 #define AZX_MAX_FRAG 32
214 /* max buffer size - no h/w limit, you can increase as you like */
215 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
216 /* max number of PCM devics per card */
217 #define AZX_MAX_PCMS 8
219 /* RIRB int mask: overrun[2], response[0] */
220 #define RIRB_INT_RESPONSE 0x01
221 #define RIRB_INT_OVERRUN 0x04
222 #define RIRB_INT_MASK 0x05
224 /* STATESTS int mask: SD2,SD1,SD0 */
225 #define AZX_MAX_CODECS 3
226 #define STATESTS_INT_MASK 0x07
229 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
230 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
231 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
232 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
233 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
234 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
235 #define SD_CTL_STREAM_TAG_SHIFT 20
237 /* SD_CTL and SD_STS */
238 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
239 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
240 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
241 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
245 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
247 /* INTCTL and INTSTS */
248 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
249 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
250 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
252 /* GCTL unsolicited response enable bit */
253 #define ICH6_GCTL_UREN (1<<8)
256 #define ICH6_GCTL_RESET (1<<0)
258 /* CORB/RIRB control, read/write pointer */
259 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
260 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
261 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
262 /* below are so far hardcoded - should read registers in future */
263 #define ICH6_MAX_CORB_ENTRIES 256
264 #define ICH6_MAX_RIRB_ENTRIES 256
266 /* position fix mode */
273 /* Defines for ATI HD Audio support in SB450 south bridge */
274 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
275 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
277 /* Defines for Nvidia HDA support */
278 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
279 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
281 /* Defines for Intel SCH HDA snoop control */
282 #define INTEL_SCH_HDA_DEVC 0x78
283 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
290 struct snd_dma_buffer bdl; /* BDL buffer */
291 u32 *posbuf; /* position buffer pointer */
293 unsigned int bufsize; /* size of the play buffer in bytes */
294 unsigned int period_bytes; /* size of the period in bytes */
295 unsigned int frags; /* number for period in the play buffer */
296 unsigned int fifo_size; /* FIFO size */
298 void __iomem *sd_addr; /* stream descriptor pointer */
300 u32 sd_int_sta_mask; /* stream int status mask */
303 struct snd_pcm_substream *substream; /* assigned substream,
306 unsigned int format_val; /* format value to be set in the
307 * controller and the codec
309 unsigned char stream_tag; /* assigned stream */
310 unsigned char index; /* stream index */
312 unsigned int opened :1;
313 unsigned int running :1;
314 unsigned int irq_pending :1;
315 unsigned int irq_ignore :1;
320 u32 *buf; /* CORB/RIRB buffer
321 * Each CORB entry is 4byte, RIRB is 8byte
323 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
325 unsigned short rp, wp; /* read/write pointers */
326 int cmds; /* number of pending requests */
327 u32 res; /* last read value */
331 struct snd_card *card;
335 /* chip type specific */
337 int playback_streams;
338 int playback_index_offset;
340 int capture_index_offset;
345 void __iomem *remap_addr;
350 struct mutex open_mutex;
352 /* streams (x num_streams) */
353 struct azx_dev *azx_dev;
356 struct snd_pcm *pcm[AZX_MAX_PCMS];
359 unsigned short codec_mask;
366 /* CORB/RIRB and position buffers */
367 struct snd_dma_buffer rb;
368 struct snd_dma_buffer posbuf;
372 unsigned int running :1;
373 unsigned int initialized :1;
374 unsigned int single_cmd :1;
375 unsigned int polling_mode :1;
377 unsigned int irq_pending_warned :1;
380 unsigned int last_cmd; /* last issued command (to sync) */
382 /* for pending irqs */
383 struct work_struct irq_pending_work;
399 static char *driver_short_names[] __devinitdata = {
400 [AZX_DRIVER_ICH] = "HDA Intel",
401 [AZX_DRIVER_SCH] = "HDA Intel MID",
402 [AZX_DRIVER_ATI] = "HDA ATI SB",
403 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
404 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
405 [AZX_DRIVER_SIS] = "HDA SIS966",
406 [AZX_DRIVER_ULI] = "HDA ULI M5461",
407 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
408 [AZX_DRIVER_TERA] = "HDA Teradici",
412 * macros for easy use
414 #define azx_writel(chip,reg,value) \
415 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
416 #define azx_readl(chip,reg) \
417 readl((chip)->remap_addr + ICH6_REG_##reg)
418 #define azx_writew(chip,reg,value) \
419 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
420 #define azx_readw(chip,reg) \
421 readw((chip)->remap_addr + ICH6_REG_##reg)
422 #define azx_writeb(chip,reg,value) \
423 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
424 #define azx_readb(chip,reg) \
425 readb((chip)->remap_addr + ICH6_REG_##reg)
427 #define azx_sd_writel(dev,reg,value) \
428 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
429 #define azx_sd_readl(dev,reg) \
430 readl((dev)->sd_addr + ICH6_REG_##reg)
431 #define azx_sd_writew(dev,reg,value) \
432 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
433 #define azx_sd_readw(dev,reg) \
434 readw((dev)->sd_addr + ICH6_REG_##reg)
435 #define azx_sd_writeb(dev,reg,value) \
436 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
437 #define azx_sd_readb(dev,reg) \
438 readb((dev)->sd_addr + ICH6_REG_##reg)
440 /* for pcm support */
441 #define get_azx_dev(substream) (substream->runtime->private_data)
443 /* Get the upper 32bit of the given dma_addr_t
444 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
446 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
448 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
451 * Interface for HD codec
455 * CORB / RIRB interface
457 static int azx_alloc_cmd_io(struct azx *chip)
461 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
462 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
463 snd_dma_pci_data(chip->pci),
464 PAGE_SIZE, &chip->rb);
466 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
472 static void azx_init_cmd_io(struct azx *chip)
475 chip->corb.addr = chip->rb.addr;
476 chip->corb.buf = (u32 *)chip->rb.area;
477 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
478 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
480 /* set the corb size to 256 entries (ULI requires explicitly) */
481 azx_writeb(chip, CORBSIZE, 0x02);
482 /* set the corb write pointer to 0 */
483 azx_writew(chip, CORBWP, 0);
484 /* reset the corb hw read pointer */
485 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
486 /* enable corb dma */
487 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
490 chip->rirb.addr = chip->rb.addr + 2048;
491 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
492 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
493 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
495 /* set the rirb size to 256 entries (ULI requires explicitly) */
496 azx_writeb(chip, RIRBSIZE, 0x02);
497 /* reset the rirb hw write pointer */
498 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
499 /* set N=1, get RIRB response interrupt for new entry */
500 azx_writew(chip, RINTCNT, 1);
501 /* enable rirb dma and response irq */
502 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
503 chip->rirb.rp = chip->rirb.cmds = 0;
506 static void azx_free_cmd_io(struct azx *chip)
508 /* disable ringbuffer DMAs */
509 azx_writeb(chip, RIRBCTL, 0);
510 azx_writeb(chip, CORBCTL, 0);
514 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
516 struct azx *chip = codec->bus->private_data;
519 /* add command to corb */
520 wp = azx_readb(chip, CORBWP);
522 wp %= ICH6_MAX_CORB_ENTRIES;
524 spin_lock_irq(&chip->reg_lock);
526 chip->corb.buf[wp] = cpu_to_le32(val);
527 azx_writel(chip, CORBWP, wp);
528 spin_unlock_irq(&chip->reg_lock);
533 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
535 /* retrieve RIRB entry - called from interrupt handler */
536 static void azx_update_rirb(struct azx *chip)
541 wp = azx_readb(chip, RIRBWP);
542 if (wp == chip->rirb.wp)
546 while (chip->rirb.rp != wp) {
548 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
550 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
551 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
552 res = le32_to_cpu(chip->rirb.buf[rp]);
553 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
554 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
555 else if (chip->rirb.cmds) {
556 chip->rirb.res = res;
563 /* receive a response */
564 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
566 struct azx *chip = codec->bus->private_data;
567 unsigned long timeout;
570 timeout = jiffies + msecs_to_jiffies(1000);
572 if (chip->polling_mode) {
573 spin_lock_irq(&chip->reg_lock);
574 azx_update_rirb(chip);
575 spin_unlock_irq(&chip->reg_lock);
577 if (!chip->rirb.cmds) {
579 return chip->rirb.res; /* the last value */
581 if (time_after(jiffies, timeout))
583 if (codec->bus->needs_damn_long_delay)
584 msleep(2); /* temporary workaround */
592 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
593 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
594 free_irq(chip->irq, chip);
596 pci_disable_msi(chip->pci);
598 if (azx_acquire_irq(chip, 1) < 0)
603 if (!chip->polling_mode) {
604 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
605 "switching to polling mode: last cmd=0x%08x\n",
607 chip->polling_mode = 1;
611 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
612 "switching to single_cmd mode: last cmd=0x%08x\n",
614 chip->rirb.rp = azx_readb(chip, RIRBWP);
616 /* switch to single_cmd mode */
617 chip->single_cmd = 1;
618 azx_free_cmd_io(chip);
623 * Use the single immediate command instead of CORB/RIRB for simplicity
625 * Note: according to Intel, this is not preferred use. The command was
626 * intended for the BIOS only, and may get confused with unsolicited
627 * responses. So, we shouldn't use it for normal operation from the
629 * I left the codes, however, for debugging/testing purposes.
633 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
635 struct azx *chip = codec->bus->private_data;
639 /* check ICB busy bit */
640 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
641 /* Clear IRV valid bit */
642 azx_writew(chip, IRS, azx_readw(chip, IRS) |
644 azx_writel(chip, IC, val);
645 azx_writew(chip, IRS, azx_readw(chip, IRS) |
651 if (printk_ratelimit())
652 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
653 azx_readw(chip, IRS), val);
657 /* receive a response */
658 static unsigned int azx_single_get_response(struct hda_codec *codec)
660 struct azx *chip = codec->bus->private_data;
664 /* check IRV busy bit */
665 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
666 return azx_readl(chip, IR);
669 if (printk_ratelimit())
670 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
671 azx_readw(chip, IRS));
672 return (unsigned int)-1;
676 * The below are the main callbacks from hda_codec.
678 * They are just the skeleton to call sub-callbacks according to the
679 * current setting of chip->single_cmd.
683 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
684 int direct, unsigned int verb,
687 struct azx *chip = codec->bus->private_data;
690 val = (u32)(codec->addr & 0x0f) << 28;
691 val |= (u32)direct << 27;
692 val |= (u32)nid << 20;
695 chip->last_cmd = val;
697 if (chip->single_cmd)
698 return azx_single_send_cmd(codec, val);
700 return azx_corb_send_cmd(codec, val);
704 static unsigned int azx_get_response(struct hda_codec *codec)
706 struct azx *chip = codec->bus->private_data;
707 if (chip->single_cmd)
708 return azx_single_get_response(codec);
710 return azx_rirb_get_response(codec);
713 #ifdef CONFIG_SND_HDA_POWER_SAVE
714 static void azx_power_notify(struct hda_codec *codec);
717 /* reset codec link */
718 static int azx_reset(struct azx *chip)
723 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
725 /* reset controller */
726 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
729 while (azx_readb(chip, GCTL) && --count)
732 /* delay for >= 100us for codec PLL to settle per spec
733 * Rev 0.9 section 5.5.1
737 /* Bring controller out of reset */
738 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
741 while (!azx_readb(chip, GCTL) && --count)
744 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
747 /* check to see if controller is ready */
748 if (!azx_readb(chip, GCTL)) {
749 snd_printd("azx_reset: controller not ready!\n");
753 /* Accept unsolicited responses */
754 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
757 if (!chip->codec_mask) {
758 chip->codec_mask = azx_readw(chip, STATESTS);
759 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
770 /* enable interrupts */
771 static void azx_int_enable(struct azx *chip)
773 /* enable controller CIE and GIE */
774 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
775 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
778 /* disable interrupts */
779 static void azx_int_disable(struct azx *chip)
783 /* disable interrupts in stream descriptor */
784 for (i = 0; i < chip->num_streams; i++) {
785 struct azx_dev *azx_dev = &chip->azx_dev[i];
786 azx_sd_writeb(azx_dev, SD_CTL,
787 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
790 /* disable SIE for all streams */
791 azx_writeb(chip, INTCTL, 0);
793 /* disable controller CIE and GIE */
794 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
795 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
798 /* clear interrupts */
799 static void azx_int_clear(struct azx *chip)
803 /* clear stream status */
804 for (i = 0; i < chip->num_streams; i++) {
805 struct azx_dev *azx_dev = &chip->azx_dev[i];
806 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
810 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
812 /* clear rirb status */
813 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
815 /* clear int status */
816 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
820 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
823 azx_writeb(chip, INTCTL,
824 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
825 /* set DMA start and interrupt mask */
826 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
827 SD_CTL_DMA_START | SD_INT_MASK);
831 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
834 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
835 ~(SD_CTL_DMA_START | SD_INT_MASK));
836 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
838 azx_writeb(chip, INTCTL,
839 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
844 * reset and start the controller registers
846 static void azx_init_chip(struct azx *chip)
848 if (chip->initialized)
851 /* reset controller */
854 /* initialize interrupts */
856 azx_int_enable(chip);
858 /* initialize the codec command I/O */
859 if (!chip->single_cmd)
860 azx_init_cmd_io(chip);
862 /* program the position buffer */
863 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
864 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
866 chip->initialized = 1;
870 * initialize the PCI registers
872 /* update bits in a PCI register byte */
873 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
874 unsigned char mask, unsigned char val)
878 pci_read_config_byte(pci, reg, &data);
880 data |= (val & mask);
881 pci_write_config_byte(pci, reg, data);
884 static void azx_init_pci(struct azx *chip)
886 unsigned short snoop;
888 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
889 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
890 * Ensuring these bits are 0 clears playback static on some HD Audio
893 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
895 switch (chip->driver_type) {
897 /* For ATI SB450 azalia HD audio, we need to enable snoop */
898 update_pci_byte(chip->pci,
899 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
900 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
902 case AZX_DRIVER_NVIDIA:
903 /* For NVIDIA HDA, enable snoop */
904 update_pci_byte(chip->pci,
905 NVIDIA_HDA_TRANSREG_ADDR,
906 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
909 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
910 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
911 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
912 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
913 pci_read_config_word(chip->pci,
914 INTEL_SCH_HDA_DEVC, &snoop);
915 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
916 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
925 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
930 static irqreturn_t azx_interrupt(int irq, void *dev_id)
932 struct azx *chip = dev_id;
933 struct azx_dev *azx_dev;
937 spin_lock(&chip->reg_lock);
939 status = azx_readl(chip, INTSTS);
941 spin_unlock(&chip->reg_lock);
945 for (i = 0; i < chip->num_streams; i++) {
946 azx_dev = &chip->azx_dev[i];
947 if (status & azx_dev->sd_int_sta_mask) {
948 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
949 if (!azx_dev->substream || !azx_dev->running)
951 /* ignore the first dummy IRQ (due to pos_adj) */
952 if (azx_dev->irq_ignore) {
953 azx_dev->irq_ignore = 0;
956 /* check whether this IRQ is really acceptable */
957 if (azx_position_ok(chip, azx_dev)) {
958 azx_dev->irq_pending = 0;
959 spin_unlock(&chip->reg_lock);
960 snd_pcm_period_elapsed(azx_dev->substream);
961 spin_lock(&chip->reg_lock);
963 /* bogus IRQ, process it later */
964 azx_dev->irq_pending = 1;
965 schedule_work(&chip->irq_pending_work);
971 status = azx_readb(chip, RIRBSTS);
972 if (status & RIRB_INT_MASK) {
973 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
974 azx_update_rirb(chip);
975 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
979 /* clear state status int */
980 if (azx_readb(chip, STATESTS) & 0x04)
981 azx_writeb(chip, STATESTS, 0x04);
983 spin_unlock(&chip->reg_lock);
992 static int setup_bdle(struct snd_pcm_substream *substream,
993 struct azx_dev *azx_dev, u32 **bdlp,
994 int ofs, int size, int with_ioc)
996 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
1003 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1006 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1007 /* program the address field of the BDL entry */
1008 bdl[0] = cpu_to_le32((u32)addr);
1009 bdl[1] = cpu_to_le32(upper_32bit(addr));
1010 /* program the size field of the BDL entry */
1011 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1014 bdl[2] = cpu_to_le32(chunk);
1015 /* program the IOC to enable interrupt
1016 * only when the whole fragment is processed
1019 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1029 * set up BDL entries
1031 static int azx_setup_periods(struct azx *chip,
1032 struct snd_pcm_substream *substream,
1033 struct azx_dev *azx_dev)
1036 int i, ofs, periods, period_bytes;
1039 /* reset BDL address */
1040 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1041 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1043 period_bytes = snd_pcm_lib_period_bytes(substream);
1044 azx_dev->period_bytes = period_bytes;
1045 periods = azx_dev->bufsize / period_bytes;
1047 /* program the initial BDL entries */
1048 bdl = (u32 *)azx_dev->bdl.area;
1051 azx_dev->irq_ignore = 0;
1052 pos_adj = bdl_pos_adj[chip->dev_index];
1054 struct snd_pcm_runtime *runtime = substream->runtime;
1055 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1058 pos_adj = frames_to_bytes(runtime, pos_adj);
1059 if (pos_adj >= period_bytes) {
1060 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1061 bdl_pos_adj[chip->dev_index]);
1064 ofs = setup_bdle(substream, azx_dev,
1065 &bdl, ofs, pos_adj, 1);
1068 azx_dev->irq_ignore = 1;
1072 for (i = 0; i < periods; i++) {
1073 if (i == periods - 1 && pos_adj)
1074 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1075 period_bytes - pos_adj, 0);
1077 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1085 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1086 azx_dev->bufsize, period_bytes);
1088 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1089 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1094 * set up the SD for streaming
1096 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1101 /* make sure the run bit is zero for SD */
1102 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1105 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1106 SD_CTL_STREAM_RESET);
1109 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1112 val &= ~SD_CTL_STREAM_RESET;
1113 azx_sd_writeb(azx_dev, SD_CTL, val);
1117 /* waiting for hardware to report that the stream is out of reset */
1118 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1122 /* program the stream_tag */
1123 azx_sd_writel(azx_dev, SD_CTL,
1124 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1125 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1127 /* program the length of samples in cyclic buffer */
1128 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1130 /* program the stream format */
1131 /* this value needs to be the same as the one programmed */
1132 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1134 /* program the stream LVI (last valid index) of the BDL */
1135 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1137 /* program the BDL address */
1138 /* lower BDL address */
1139 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1140 /* upper BDL address */
1141 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1143 /* enable the position buffer */
1144 if (chip->position_fix == POS_FIX_POSBUF ||
1145 chip->position_fix == POS_FIX_AUTO) {
1146 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1147 azx_writel(chip, DPLBASE,
1148 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1151 /* set the interrupt enable bits in the descriptor control register */
1152 azx_sd_writel(azx_dev, SD_CTL,
1153 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1160 * Codec initialization
1163 static unsigned int azx_max_codecs[] __devinitdata = {
1164 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */
1165 [AZX_DRIVER_SCH] = 3,
1166 [AZX_DRIVER_ATI] = 4,
1167 [AZX_DRIVER_ATIHDMI] = 4,
1168 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1169 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1170 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1171 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1172 [AZX_DRIVER_TERA] = 1,
1175 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1176 unsigned int codec_probe_mask)
1178 struct hda_bus_template bus_temp;
1179 int c, codecs, audio_codecs, err;
1181 memset(&bus_temp, 0, sizeof(bus_temp));
1182 bus_temp.private_data = chip;
1183 bus_temp.modelname = model;
1184 bus_temp.pci = chip->pci;
1185 bus_temp.ops.command = azx_send_cmd;
1186 bus_temp.ops.get_response = azx_get_response;
1187 #ifdef CONFIG_SND_HDA_POWER_SAVE
1188 bus_temp.ops.pm_notify = azx_power_notify;
1191 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1195 codecs = audio_codecs = 0;
1196 for (c = 0; c < AZX_MAX_CODECS; c++) {
1197 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1198 struct hda_codec *codec;
1199 err = snd_hda_codec_new(chip->bus, c, &codec);
1207 if (!audio_codecs) {
1208 /* probe additional slots if no codec is found */
1209 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1210 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1211 err = snd_hda_codec_new(chip->bus, c, NULL);
1219 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1231 /* assign a stream for the PCM */
1232 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1235 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1236 dev = chip->playback_index_offset;
1237 nums = chip->playback_streams;
1239 dev = chip->capture_index_offset;
1240 nums = chip->capture_streams;
1242 for (i = 0; i < nums; i++, dev++)
1243 if (!chip->azx_dev[dev].opened) {
1244 chip->azx_dev[dev].opened = 1;
1245 return &chip->azx_dev[dev];
1250 /* release the assigned stream */
1251 static inline void azx_release_device(struct azx_dev *azx_dev)
1253 azx_dev->opened = 0;
1256 static struct snd_pcm_hardware azx_pcm_hw = {
1257 .info = (SNDRV_PCM_INFO_MMAP |
1258 SNDRV_PCM_INFO_INTERLEAVED |
1259 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1260 SNDRV_PCM_INFO_MMAP_VALID |
1261 /* No full-resume yet implemented */
1262 /* SNDRV_PCM_INFO_RESUME |*/
1263 SNDRV_PCM_INFO_PAUSE |
1264 SNDRV_PCM_INFO_SYNC_START),
1265 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1266 .rates = SNDRV_PCM_RATE_48000,
1271 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1272 .period_bytes_min = 128,
1273 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1275 .periods_max = AZX_MAX_FRAG,
1281 struct hda_codec *codec;
1282 struct hda_pcm_stream *hinfo[2];
1285 static int azx_pcm_open(struct snd_pcm_substream *substream)
1287 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1288 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1289 struct azx *chip = apcm->chip;
1290 struct azx_dev *azx_dev;
1291 struct snd_pcm_runtime *runtime = substream->runtime;
1292 unsigned long flags;
1295 mutex_lock(&chip->open_mutex);
1296 azx_dev = azx_assign_device(chip, substream->stream);
1297 if (azx_dev == NULL) {
1298 mutex_unlock(&chip->open_mutex);
1301 runtime->hw = azx_pcm_hw;
1302 runtime->hw.channels_min = hinfo->channels_min;
1303 runtime->hw.channels_max = hinfo->channels_max;
1304 runtime->hw.formats = hinfo->formats;
1305 runtime->hw.rates = hinfo->rates;
1306 snd_pcm_limit_hw_rates(runtime);
1307 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1308 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1310 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1312 snd_hda_power_up(apcm->codec);
1313 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1315 azx_release_device(azx_dev);
1316 snd_hda_power_down(apcm->codec);
1317 mutex_unlock(&chip->open_mutex);
1320 spin_lock_irqsave(&chip->reg_lock, flags);
1321 azx_dev->substream = substream;
1322 azx_dev->running = 0;
1323 spin_unlock_irqrestore(&chip->reg_lock, flags);
1325 runtime->private_data = azx_dev;
1326 snd_pcm_set_sync(substream);
1327 mutex_unlock(&chip->open_mutex);
1331 static int azx_pcm_close(struct snd_pcm_substream *substream)
1333 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1334 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1335 struct azx *chip = apcm->chip;
1336 struct azx_dev *azx_dev = get_azx_dev(substream);
1337 unsigned long flags;
1339 mutex_lock(&chip->open_mutex);
1340 spin_lock_irqsave(&chip->reg_lock, flags);
1341 azx_dev->substream = NULL;
1342 azx_dev->running = 0;
1343 spin_unlock_irqrestore(&chip->reg_lock, flags);
1344 azx_release_device(azx_dev);
1345 hinfo->ops.close(hinfo, apcm->codec, substream);
1346 snd_hda_power_down(apcm->codec);
1347 mutex_unlock(&chip->open_mutex);
1351 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1352 struct snd_pcm_hw_params *hw_params)
1354 return snd_pcm_lib_malloc_pages(substream,
1355 params_buffer_bytes(hw_params));
1358 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1360 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1361 struct azx_dev *azx_dev = get_azx_dev(substream);
1362 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1364 /* reset BDL address */
1365 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1366 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1367 azx_sd_writel(azx_dev, SD_CTL, 0);
1369 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1371 return snd_pcm_lib_free_pages(substream);
1374 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1376 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1377 struct azx *chip = apcm->chip;
1378 struct azx_dev *azx_dev = get_azx_dev(substream);
1379 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1380 struct snd_pcm_runtime *runtime = substream->runtime;
1382 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1383 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1387 if (!azx_dev->format_val) {
1388 snd_printk(KERN_ERR SFX
1389 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1390 runtime->rate, runtime->channels, runtime->format);
1394 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1395 azx_dev->bufsize, azx_dev->format_val);
1396 if (azx_setup_periods(chip, substream, azx_dev) < 0)
1398 azx_setup_controller(chip, azx_dev);
1399 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1400 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1402 azx_dev->fifo_size = 0;
1404 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1405 azx_dev->format_val, substream);
1408 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1410 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1411 struct azx *chip = apcm->chip;
1412 struct azx_dev *azx_dev;
1413 struct snd_pcm_substream *s;
1414 int start, nsync = 0, sbits = 0;
1418 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1419 case SNDRV_PCM_TRIGGER_RESUME:
1420 case SNDRV_PCM_TRIGGER_START:
1423 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1424 case SNDRV_PCM_TRIGGER_SUSPEND:
1425 case SNDRV_PCM_TRIGGER_STOP:
1432 snd_pcm_group_for_each_entry(s, substream) {
1433 if (s->pcm->card != substream->pcm->card)
1435 azx_dev = get_azx_dev(s);
1436 sbits |= 1 << azx_dev->index;
1438 snd_pcm_trigger_done(s, substream);
1441 spin_lock(&chip->reg_lock);
1443 /* first, set SYNC bits of corresponding streams */
1444 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1446 snd_pcm_group_for_each_entry(s, substream) {
1447 if (s->pcm->card != substream->pcm->card)
1449 azx_dev = get_azx_dev(s);
1451 azx_stream_start(chip, azx_dev);
1453 azx_stream_stop(chip, azx_dev);
1454 azx_dev->running = start;
1456 spin_unlock(&chip->reg_lock);
1460 /* wait until all FIFOs get ready */
1461 for (timeout = 5000; timeout; timeout--) {
1463 snd_pcm_group_for_each_entry(s, substream) {
1464 if (s->pcm->card != substream->pcm->card)
1466 azx_dev = get_azx_dev(s);
1467 if (!(azx_sd_readb(azx_dev, SD_STS) &
1476 /* wait until all RUN bits are cleared */
1477 for (timeout = 5000; timeout; timeout--) {
1479 snd_pcm_group_for_each_entry(s, substream) {
1480 if (s->pcm->card != substream->pcm->card)
1482 azx_dev = get_azx_dev(s);
1483 if (azx_sd_readb(azx_dev, SD_CTL) &
1493 spin_lock(&chip->reg_lock);
1494 /* reset SYNC bits */
1495 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1496 spin_unlock(&chip->reg_lock);
1501 static unsigned int azx_get_position(struct azx *chip,
1502 struct azx_dev *azx_dev)
1506 if (chip->position_fix == POS_FIX_POSBUF ||
1507 chip->position_fix == POS_FIX_AUTO) {
1508 /* use the position buffer */
1509 pos = le32_to_cpu(*azx_dev->posbuf);
1512 pos = azx_sd_readl(azx_dev, SD_LPIB);
1514 if (pos >= azx_dev->bufsize)
1519 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1521 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1522 struct azx *chip = apcm->chip;
1523 struct azx_dev *azx_dev = get_azx_dev(substream);
1524 return bytes_to_frames(substream->runtime,
1525 azx_get_position(chip, azx_dev));
1529 * Check whether the current DMA position is acceptable for updating
1530 * periods. Returns non-zero if it's OK.
1532 * Many HD-audio controllers appear pretty inaccurate about
1533 * the update-IRQ timing. The IRQ is issued before actually the
1534 * data is processed. So, we need to process it afterwords in a
1537 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1541 pos = azx_get_position(chip, azx_dev);
1542 if (chip->position_fix == POS_FIX_AUTO) {
1545 "hda-intel: Invalid position buffer, "
1546 "using LPIB read method instead.\n");
1547 chip->position_fix = POS_FIX_LPIB;
1548 pos = azx_get_position(chip, azx_dev);
1550 chip->position_fix = POS_FIX_POSBUF;
1553 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1554 return 0; /* NG - it's below the period boundary */
1555 return 1; /* OK, it's fine */
1559 * The work for pending PCM period updates.
1561 static void azx_irq_pending_work(struct work_struct *work)
1563 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1566 if (!chip->irq_pending_warned) {
1568 "hda-intel: IRQ timing workaround is activated "
1569 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1570 chip->card->number);
1571 chip->irq_pending_warned = 1;
1576 spin_lock_irq(&chip->reg_lock);
1577 for (i = 0; i < chip->num_streams; i++) {
1578 struct azx_dev *azx_dev = &chip->azx_dev[i];
1579 if (!azx_dev->irq_pending ||
1580 !azx_dev->substream ||
1583 if (azx_position_ok(chip, azx_dev)) {
1584 azx_dev->irq_pending = 0;
1585 spin_unlock(&chip->reg_lock);
1586 snd_pcm_period_elapsed(azx_dev->substream);
1587 spin_lock(&chip->reg_lock);
1591 spin_unlock_irq(&chip->reg_lock);
1598 /* clear irq_pending flags and assure no on-going workq */
1599 static void azx_clear_irq_pending(struct azx *chip)
1603 spin_lock_irq(&chip->reg_lock);
1604 for (i = 0; i < chip->num_streams; i++)
1605 chip->azx_dev[i].irq_pending = 0;
1606 spin_unlock_irq(&chip->reg_lock);
1607 flush_scheduled_work();
1610 static struct snd_pcm_ops azx_pcm_ops = {
1611 .open = azx_pcm_open,
1612 .close = azx_pcm_close,
1613 .ioctl = snd_pcm_lib_ioctl,
1614 .hw_params = azx_pcm_hw_params,
1615 .hw_free = azx_pcm_hw_free,
1616 .prepare = azx_pcm_prepare,
1617 .trigger = azx_pcm_trigger,
1618 .pointer = azx_pcm_pointer,
1619 .page = snd_pcm_sgbuf_ops_page,
1622 static void azx_pcm_free(struct snd_pcm *pcm)
1624 kfree(pcm->private_data);
1627 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1628 struct hda_pcm *cpcm)
1631 struct snd_pcm *pcm;
1632 struct azx_pcm *apcm;
1634 /* if no substreams are defined for both playback and capture,
1635 * it's just a placeholder. ignore it.
1637 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1640 snd_assert(cpcm->name, return -EINVAL);
1642 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1643 cpcm->stream[0].substreams,
1644 cpcm->stream[1].substreams,
1648 strcpy(pcm->name, cpcm->name);
1649 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1653 apcm->codec = codec;
1654 apcm->hinfo[0] = &cpcm->stream[0];
1655 apcm->hinfo[1] = &cpcm->stream[1];
1656 pcm->private_data = apcm;
1657 pcm->private_free = azx_pcm_free;
1658 if (cpcm->stream[0].substreams)
1659 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1660 if (cpcm->stream[1].substreams)
1661 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1662 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1663 snd_dma_pci_data(chip->pci),
1664 1024 * 64, 1024 * 1024);
1665 chip->pcm[cpcm->device] = pcm;
1669 static int __devinit azx_pcm_create(struct azx *chip)
1671 static const char *dev_name[HDA_PCM_NTYPES] = {
1672 "Audio", "SPDIF", "HDMI", "Modem"
1674 /* starting device index for each PCM type */
1675 static int dev_idx[HDA_PCM_NTYPES] = {
1676 [HDA_PCM_TYPE_AUDIO] = 0,
1677 [HDA_PCM_TYPE_SPDIF] = 1,
1678 [HDA_PCM_TYPE_HDMI] = 3,
1679 [HDA_PCM_TYPE_MODEM] = 6
1681 /* normal audio device indices; not linear to keep compatibility */
1682 static int audio_idx[4] = { 0, 2, 4, 5 };
1683 struct hda_codec *codec;
1685 int num_devs[HDA_PCM_NTYPES];
1687 err = snd_hda_build_pcms(chip->bus);
1691 /* create audio PCMs */
1692 memset(num_devs, 0, sizeof(num_devs));
1693 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1694 for (c = 0; c < codec->num_pcms; c++) {
1695 struct hda_pcm *cpcm = &codec->pcm_info[c];
1696 int type = cpcm->pcm_type;
1698 case HDA_PCM_TYPE_AUDIO:
1699 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1700 snd_printk(KERN_WARNING
1701 "Too many audio devices\n");
1704 cpcm->device = audio_idx[num_devs[type]];
1706 case HDA_PCM_TYPE_SPDIF:
1707 case HDA_PCM_TYPE_HDMI:
1708 case HDA_PCM_TYPE_MODEM:
1709 if (num_devs[type]) {
1710 snd_printk(KERN_WARNING
1711 "%s already defined\n",
1715 cpcm->device = dev_idx[type];
1718 snd_printk(KERN_WARNING
1719 "Invalid PCM type %d\n", type);
1723 err = create_codec_pcm(chip, codec, cpcm);
1732 * mixer creation - all stuff is implemented in hda module
1734 static int __devinit azx_mixer_create(struct azx *chip)
1736 return snd_hda_build_controls(chip->bus);
1741 * initialize SD streams
1743 static int __devinit azx_init_stream(struct azx *chip)
1747 /* initialize each stream (aka device)
1748 * assign the starting bdl address to each stream (device)
1751 for (i = 0; i < chip->num_streams; i++) {
1752 struct azx_dev *azx_dev = &chip->azx_dev[i];
1753 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1754 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1755 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1756 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1757 azx_dev->sd_int_sta_mask = 1 << i;
1758 /* stream tag: must be non-zero and unique */
1760 azx_dev->stream_tag = i + 1;
1766 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1768 if (request_irq(chip->pci->irq, azx_interrupt,
1769 chip->msi ? 0 : IRQF_SHARED,
1770 "HDA Intel", chip)) {
1771 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1772 "disabling device\n", chip->pci->irq);
1774 snd_card_disconnect(chip->card);
1777 chip->irq = chip->pci->irq;
1778 pci_intx(chip->pci, !chip->msi);
1783 static void azx_stop_chip(struct azx *chip)
1785 if (!chip->initialized)
1788 /* disable interrupts */
1789 azx_int_disable(chip);
1790 azx_int_clear(chip);
1792 /* disable CORB/RIRB */
1793 azx_free_cmd_io(chip);
1795 /* disable position buffer */
1796 azx_writel(chip, DPLBASE, 0);
1797 azx_writel(chip, DPUBASE, 0);
1799 chip->initialized = 0;
1802 #ifdef CONFIG_SND_HDA_POWER_SAVE
1803 /* power-up/down the controller */
1804 static void azx_power_notify(struct hda_codec *codec)
1806 struct azx *chip = codec->bus->private_data;
1807 struct hda_codec *c;
1810 list_for_each_entry(c, &codec->bus->codec_list, list) {
1817 azx_init_chip(chip);
1818 else if (chip->running && power_save_controller)
1819 azx_stop_chip(chip);
1821 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1827 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1829 struct snd_card *card = pci_get_drvdata(pci);
1830 struct azx *chip = card->private_data;
1833 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1834 azx_clear_irq_pending(chip);
1835 for (i = 0; i < AZX_MAX_PCMS; i++)
1836 snd_pcm_suspend_all(chip->pcm[i]);
1837 if (chip->initialized)
1838 snd_hda_suspend(chip->bus, state);
1839 azx_stop_chip(chip);
1840 if (chip->irq >= 0) {
1841 free_irq(chip->irq, chip);
1845 pci_disable_msi(chip->pci);
1846 pci_disable_device(pci);
1847 pci_save_state(pci);
1848 pci_set_power_state(pci, pci_choose_state(pci, state));
1852 static int azx_resume(struct pci_dev *pci)
1854 struct snd_card *card = pci_get_drvdata(pci);
1855 struct azx *chip = card->private_data;
1857 pci_set_power_state(pci, PCI_D0);
1858 pci_restore_state(pci);
1859 if (pci_enable_device(pci) < 0) {
1860 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1861 "disabling device\n");
1862 snd_card_disconnect(card);
1865 pci_set_master(pci);
1867 if (pci_enable_msi(pci) < 0)
1869 if (azx_acquire_irq(chip, 1) < 0)
1873 if (snd_hda_codecs_inuse(chip->bus))
1874 azx_init_chip(chip);
1876 snd_hda_resume(chip->bus);
1877 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1880 #endif /* CONFIG_PM */
1886 static int azx_free(struct azx *chip)
1890 if (chip->initialized) {
1891 azx_clear_irq_pending(chip);
1892 for (i = 0; i < chip->num_streams; i++)
1893 azx_stream_stop(chip, &chip->azx_dev[i]);
1894 azx_stop_chip(chip);
1898 free_irq(chip->irq, (void*)chip);
1900 pci_disable_msi(chip->pci);
1901 if (chip->remap_addr)
1902 iounmap(chip->remap_addr);
1904 if (chip->azx_dev) {
1905 for (i = 0; i < chip->num_streams; i++)
1906 if (chip->azx_dev[i].bdl.area)
1907 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1910 snd_dma_free_pages(&chip->rb);
1911 if (chip->posbuf.area)
1912 snd_dma_free_pages(&chip->posbuf);
1913 pci_release_regions(chip->pci);
1914 pci_disable_device(chip->pci);
1915 kfree(chip->azx_dev);
1921 static int azx_dev_free(struct snd_device *device)
1923 return azx_free(device->device_data);
1927 * white/black-listing for position_fix
1929 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1930 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1931 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1932 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1936 static int __devinit check_position_fix(struct azx *chip, int fix)
1938 const struct snd_pci_quirk *q;
1940 if (fix == POS_FIX_AUTO) {
1941 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1944 "hda_intel: position_fix set to %d "
1945 "for device %04x:%04x\n",
1946 q->value, q->subvendor, q->subdevice);
1954 * black-lists for probe_mask
1956 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1957 /* Thinkpad often breaks the controller communication when accessing
1958 * to the non-working (or non-existing) modem codec slot.
1960 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1961 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1962 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1966 static void __devinit check_probe_mask(struct azx *chip, int dev)
1968 const struct snd_pci_quirk *q;
1970 if (probe_mask[dev] == -1) {
1971 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1974 "hda_intel: probe_mask set to 0x%x "
1975 "for device %04x:%04x\n",
1976 q->value, q->subvendor, q->subdevice);
1977 probe_mask[dev] = q->value;
1986 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1987 int dev, int driver_type,
1992 unsigned short gcap;
1993 static struct snd_device_ops ops = {
1994 .dev_free = azx_dev_free,
1999 err = pci_enable_device(pci);
2003 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2005 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2006 pci_disable_device(pci);
2010 spin_lock_init(&chip->reg_lock);
2011 mutex_init(&chip->open_mutex);
2015 chip->driver_type = driver_type;
2016 chip->msi = enable_msi;
2017 chip->dev_index = dev;
2018 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2020 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2021 check_probe_mask(chip, dev);
2023 chip->single_cmd = single_cmd;
2025 if (bdl_pos_adj[dev] < 0) {
2026 switch (chip->driver_type) {
2027 case AZX_DRIVER_ICH:
2028 bdl_pos_adj[dev] = 1;
2031 bdl_pos_adj[dev] = 32;
2036 #if BITS_PER_LONG != 64
2037 /* Fix up base address on ULI M5461 */
2038 if (chip->driver_type == AZX_DRIVER_ULI) {
2040 pci_read_config_word(pci, 0x40, &tmp3);
2041 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2042 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2046 err = pci_request_regions(pci, "ICH HD audio");
2049 pci_disable_device(pci);
2053 chip->addr = pci_resource_start(pci, 0);
2054 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2055 if (chip->remap_addr == NULL) {
2056 snd_printk(KERN_ERR SFX "ioremap error\n");
2062 if (pci_enable_msi(pci) < 0)
2065 if (azx_acquire_irq(chip, 0) < 0) {
2070 pci_set_master(pci);
2071 synchronize_irq(chip->irq);
2073 gcap = azx_readw(chip, GCAP);
2074 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2076 /* allow 64bit DMA address if supported by H/W */
2077 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2078 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2080 /* read number of streams from GCAP register instead of using
2083 chip->capture_streams = (gcap >> 8) & 0x0f;
2084 chip->playback_streams = (gcap >> 12) & 0x0f;
2085 if (!chip->playback_streams && !chip->capture_streams) {
2086 /* gcap didn't give any info, switching to old method */
2088 switch (chip->driver_type) {
2089 case AZX_DRIVER_ULI:
2090 chip->playback_streams = ULI_NUM_PLAYBACK;
2091 chip->capture_streams = ULI_NUM_CAPTURE;
2093 case AZX_DRIVER_ATIHDMI:
2094 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2095 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2098 chip->playback_streams = ICH6_NUM_PLAYBACK;
2099 chip->capture_streams = ICH6_NUM_CAPTURE;
2103 chip->capture_index_offset = 0;
2104 chip->playback_index_offset = chip->capture_streams;
2105 chip->num_streams = chip->playback_streams + chip->capture_streams;
2106 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2108 if (!chip->azx_dev) {
2109 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2113 for (i = 0; i < chip->num_streams; i++) {
2114 /* allocate memory for the BDL for each stream */
2115 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2116 snd_dma_pci_data(chip->pci),
2117 BDL_SIZE, &chip->azx_dev[i].bdl);
2119 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2123 /* allocate memory for the position buffer */
2124 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2125 snd_dma_pci_data(chip->pci),
2126 chip->num_streams * 8, &chip->posbuf);
2128 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2131 /* allocate CORB/RIRB */
2132 if (!chip->single_cmd) {
2133 err = azx_alloc_cmd_io(chip);
2138 /* initialize streams */
2139 azx_init_stream(chip);
2141 /* initialize chip */
2143 azx_init_chip(chip);
2145 /* codec detection */
2146 if (!chip->codec_mask) {
2147 snd_printk(KERN_ERR SFX "no codecs found!\n");
2152 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2154 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2158 strcpy(card->driver, "HDA-Intel");
2159 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2160 sprintf(card->longname, "%s at 0x%lx irq %i",
2161 card->shortname, chip->addr, chip->irq);
2171 static void power_down_all_codecs(struct azx *chip)
2173 #ifdef CONFIG_SND_HDA_POWER_SAVE
2174 /* The codecs were powered up in snd_hda_codec_new().
2175 * Now all initialization done, so turn them down if possible
2177 struct hda_codec *codec;
2178 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2179 snd_hda_power_down(codec);
2184 static int __devinit azx_probe(struct pci_dev *pci,
2185 const struct pci_device_id *pci_id)
2188 struct snd_card *card;
2192 if (dev >= SNDRV_CARDS)
2199 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2201 snd_printk(KERN_ERR SFX "Error creating card!\n");
2205 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2207 snd_card_free(card);
2210 card->private_data = chip;
2212 /* create codec instances */
2213 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2215 snd_card_free(card);
2219 /* create PCM streams */
2220 err = azx_pcm_create(chip);
2222 snd_card_free(card);
2226 /* create mixer controls */
2227 err = azx_mixer_create(chip);
2229 snd_card_free(card);
2233 snd_card_set_dev(card, &pci->dev);
2235 err = snd_card_register(card);
2237 snd_card_free(card);
2241 pci_set_drvdata(pci, card);
2243 power_down_all_codecs(chip);
2249 static void __devexit azx_remove(struct pci_dev *pci)
2251 snd_card_free(pci_get_drvdata(pci));
2252 pci_set_drvdata(pci, NULL);
2256 static struct pci_device_id azx_ids[] = {
2258 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2259 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2260 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2261 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2262 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2263 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2264 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2265 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2266 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2268 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2269 /* ATI SB 450/600 */
2270 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2271 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2273 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2274 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2275 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2276 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2277 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2278 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2279 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2280 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2281 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2282 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2283 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2284 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2285 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2286 /* VIA VT8251/VT8237A */
2287 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2289 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2291 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2293 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2294 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2295 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2296 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2297 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2298 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2299 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2300 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2301 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2302 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2303 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2304 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2305 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2306 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2307 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2308 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2309 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2310 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2311 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2312 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2313 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2314 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2316 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2319 MODULE_DEVICE_TABLE(pci, azx_ids);
2321 /* pci_driver definition */
2322 static struct pci_driver driver = {
2323 .name = "HDA Intel",
2324 .id_table = azx_ids,
2326 .remove = __devexit_p(azx_remove),
2328 .suspend = azx_suspend,
2329 .resume = azx_resume,
2333 static int __init alsa_card_azx_init(void)
2335 return pci_register_driver(&driver);
2338 static void __exit alsa_card_azx_exit(void)
2340 pci_unregister_driver(&driver);
2343 module_init(alsa_card_azx_init)
2344 module_exit(alsa_card_azx_exit)