3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/module.h>
41 #include <linux/moduleparam.h>
42 #include <linux/init.h>
43 #include <linux/slab.h>
44 #include <linux/pci.h>
45 #include <sound/core.h>
46 #include <sound/initval.h>
47 #include "hda_codec.h"
50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
53 static char *model[SNDRV_CARDS];
54 static int position_fix[SNDRV_CARDS];
56 module_param_array(index, int, NULL, 0444);
57 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
58 module_param_array(id, charp, NULL, 0444);
59 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
60 module_param_array(enable, bool, NULL, 0444);
61 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
62 module_param_array(model, charp, NULL, 0444);
63 MODULE_PARM_DESC(model, "Use the given board model.");
64 module_param_array(position_fix, int, NULL, 0444);
65 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF).");
67 MODULE_LICENSE("GPL");
68 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
76 MODULE_DESCRIPTION("Intel HDA driver");
78 #define SFX "hda-intel: "
83 #define ICH6_REG_GCAP 0x00
84 #define ICH6_REG_VMIN 0x02
85 #define ICH6_REG_VMAJ 0x03
86 #define ICH6_REG_OUTPAY 0x04
87 #define ICH6_REG_INPAY 0x06
88 #define ICH6_REG_GCTL 0x08
89 #define ICH6_REG_WAKEEN 0x0c
90 #define ICH6_REG_STATESTS 0x0e
91 #define ICH6_REG_GSTS 0x10
92 #define ICH6_REG_INTCTL 0x20
93 #define ICH6_REG_INTSTS 0x24
94 #define ICH6_REG_WALCLK 0x30
95 #define ICH6_REG_SYNC 0x34
96 #define ICH6_REG_CORBLBASE 0x40
97 #define ICH6_REG_CORBUBASE 0x44
98 #define ICH6_REG_CORBWP 0x48
99 #define ICH6_REG_CORBRP 0x4A
100 #define ICH6_REG_CORBCTL 0x4c
101 #define ICH6_REG_CORBSTS 0x4d
102 #define ICH6_REG_CORBSIZE 0x4e
104 #define ICH6_REG_RIRBLBASE 0x50
105 #define ICH6_REG_RIRBUBASE 0x54
106 #define ICH6_REG_RIRBWP 0x58
107 #define ICH6_REG_RINTCNT 0x5a
108 #define ICH6_REG_RIRBCTL 0x5c
109 #define ICH6_REG_RIRBSTS 0x5d
110 #define ICH6_REG_RIRBSIZE 0x5e
112 #define ICH6_REG_IC 0x60
113 #define ICH6_REG_IR 0x64
114 #define ICH6_REG_IRS 0x68
115 #define ICH6_IRS_VALID (1<<1)
116 #define ICH6_IRS_BUSY (1<<0)
118 #define ICH6_REG_DPLBASE 0x70
119 #define ICH6_REG_DPUBASE 0x74
120 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
122 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
123 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
125 /* stream register offsets from stream base */
126 #define ICH6_REG_SD_CTL 0x00
127 #define ICH6_REG_SD_STS 0x03
128 #define ICH6_REG_SD_LPIB 0x04
129 #define ICH6_REG_SD_CBL 0x08
130 #define ICH6_REG_SD_LVI 0x0c
131 #define ICH6_REG_SD_FIFOW 0x0e
132 #define ICH6_REG_SD_FIFOSIZE 0x10
133 #define ICH6_REG_SD_FORMAT 0x12
134 #define ICH6_REG_SD_BDLPL 0x18
135 #define ICH6_REG_SD_BDLPU 0x1c
138 #define ICH6_PCIREG_TCSEL 0x44
144 /* max number of SDs */
145 #define MAX_ICH6_DEV 8
146 /* max number of fragments - we may use more if allocating more pages for BDL */
147 #define AZX_MAX_FRAG (PAGE_SIZE / (MAX_ICH6_DEV * 16))
148 /* max buffer size - no h/w limit, you can increase as you like */
149 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
150 /* max number of PCM devics per card */
151 #define AZX_MAX_PCMS 8
153 /* RIRB int mask: overrun[2], response[0] */
154 #define RIRB_INT_RESPONSE 0x01
155 #define RIRB_INT_OVERRUN 0x04
156 #define RIRB_INT_MASK 0x05
158 /* STATESTS int mask: SD2,SD1,SD0 */
159 #define STATESTS_INT_MASK 0x07
160 #define AZX_MAX_CODECS 4
163 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
164 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
165 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
166 #define SD_CTL_STREAM_TAG_SHIFT 20
168 /* SD_CTL and SD_STS */
169 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
170 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
171 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
172 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
175 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
177 /* INTCTL and INTSTS */
178 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
179 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
180 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
182 /* GCTL unsolicited response enable bit */
183 #define ICH6_GCTL_UREN (1<<8)
186 #define ICH6_GCTL_RESET (1<<0)
188 /* CORB/RIRB control, read/write pointer */
189 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
190 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
191 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
192 /* below are so far hardcoded - should read registers in future */
193 #define ICH6_MAX_CORB_ENTRIES 256
194 #define ICH6_MAX_RIRB_ENTRIES 256
196 /* position fix mode */
203 /* Defines for ATI HD Audio support in SB450 south bridge */
204 #define ATI_SB450_HDAUDIO_PCI_DEVICE_ID 0x437b
205 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
206 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
210 * Use CORB/RIRB for communication from/to codecs.
211 * This is the way recommended by Intel (see below).
213 #define USE_CORB_RIRB
218 typedef struct snd_azx azx_t;
219 typedef struct snd_azx_rb azx_rb_t;
220 typedef struct snd_azx_dev azx_dev_t;
223 u32 *bdl; /* virtual address of the BDL */
224 dma_addr_t bdl_addr; /* physical address of the BDL */
225 volatile u32 *posbuf; /* position buffer pointer */
227 unsigned int bufsize; /* size of the play buffer in bytes */
228 unsigned int fragsize; /* size of each period in bytes */
229 unsigned int frags; /* number for period in the play buffer */
230 unsigned int fifo_size; /* FIFO size */
232 void __iomem *sd_addr; /* stream descriptor pointer */
234 u32 sd_int_sta_mask; /* stream int status mask */
237 snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
238 unsigned int format_val; /* format value to be set in the controller and the codec */
239 unsigned char stream_tag; /* assigned stream */
240 unsigned char index; /* stream index */
242 unsigned int opened: 1;
243 unsigned int running: 1;
248 u32 *buf; /* CORB/RIRB buffer
249 * Each CORB entry is 4byte, RIRB is 8byte
251 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
253 unsigned short rp, wp; /* read/write pointers */
254 int cmds; /* number of pending requests */
255 u32 res; /* last read value */
264 void __iomem *remap_addr;
269 struct semaphore open_mutex;
272 azx_dev_t azx_dev[MAX_ICH6_DEV];
275 unsigned int pcm_devs;
276 snd_pcm_t *pcm[AZX_MAX_PCMS];
279 unsigned short codec_mask;
286 /* BDL, CORB/RIRB and position buffers */
287 struct snd_dma_buffer bdl;
288 struct snd_dma_buffer rb;
289 struct snd_dma_buffer posbuf;
293 unsigned int initialized: 1;
297 * macros for easy use
299 #define azx_writel(chip,reg,value) \
300 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
301 #define azx_readl(chip,reg) \
302 readl((chip)->remap_addr + ICH6_REG_##reg)
303 #define azx_writew(chip,reg,value) \
304 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
305 #define azx_readw(chip,reg) \
306 readw((chip)->remap_addr + ICH6_REG_##reg)
307 #define azx_writeb(chip,reg,value) \
308 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
309 #define azx_readb(chip,reg) \
310 readb((chip)->remap_addr + ICH6_REG_##reg)
312 #define azx_sd_writel(dev,reg,value) \
313 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
314 #define azx_sd_readl(dev,reg) \
315 readl((dev)->sd_addr + ICH6_REG_##reg)
316 #define azx_sd_writew(dev,reg,value) \
317 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
318 #define azx_sd_readw(dev,reg) \
319 readw((dev)->sd_addr + ICH6_REG_##reg)
320 #define azx_sd_writeb(dev,reg,value) \
321 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
322 #define azx_sd_readb(dev,reg) \
323 readb((dev)->sd_addr + ICH6_REG_##reg)
325 /* for pcm support */
326 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
328 /* Get the upper 32bit of the given dma_addr_t
329 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
331 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
335 * Interface for HD codec
340 * CORB / RIRB interface
342 static int azx_alloc_cmd_io(azx_t *chip)
346 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
347 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
348 PAGE_SIZE, &chip->rb);
350 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
356 static void azx_init_cmd_io(azx_t *chip)
359 chip->corb.addr = chip->rb.addr;
360 chip->corb.buf = (u32 *)chip->rb.area;
361 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
362 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
364 /* set the corb write pointer to 0 */
365 azx_writew(chip, CORBWP, 0);
366 /* reset the corb hw read pointer */
367 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
368 /* enable corb dma */
369 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
372 chip->rirb.addr = chip->rb.addr + 2048;
373 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
374 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
375 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
377 /* reset the rirb hw write pointer */
378 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
379 /* set N=1, get RIRB response interrupt for new entry */
380 azx_writew(chip, RINTCNT, 1);
381 /* enable rirb dma and response irq */
383 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
385 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
387 chip->rirb.rp = chip->rirb.cmds = 0;
390 static void azx_free_cmd_io(azx_t *chip)
392 /* disable ringbuffer DMAs */
393 azx_writeb(chip, RIRBCTL, 0);
394 azx_writeb(chip, CORBCTL, 0);
398 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
399 unsigned int verb, unsigned int para)
401 azx_t *chip = codec->bus->private_data;
405 val = (u32)(codec->addr & 0x0f) << 28;
406 val |= (u32)direct << 27;
407 val |= (u32)nid << 20;
411 /* add command to corb */
412 wp = azx_readb(chip, CORBWP);
414 wp %= ICH6_MAX_CORB_ENTRIES;
416 spin_lock_irq(&chip->reg_lock);
418 chip->corb.buf[wp] = cpu_to_le32(val);
419 azx_writel(chip, CORBWP, wp);
420 spin_unlock_irq(&chip->reg_lock);
425 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
427 /* retrieve RIRB entry - called from interrupt handler */
428 static void azx_update_rirb(azx_t *chip)
433 wp = azx_readb(chip, RIRBWP);
434 if (wp == chip->rirb.wp)
438 while (chip->rirb.rp != wp) {
440 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
442 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
443 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
444 res = le32_to_cpu(chip->rirb.buf[rp]);
445 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
446 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
447 else if (chip->rirb.cmds) {
449 chip->rirb.res = res;
454 /* receive a response */
455 static unsigned int azx_get_response(struct hda_codec *codec)
457 azx_t *chip = codec->bus->private_data;
460 while (chip->rirb.cmds) {
462 snd_printk(KERN_ERR "azx_get_response timeout\n");
463 chip->rirb.rp = azx_readb(chip, RIRBWP);
469 return chip->rirb.res; /* the last value */
474 * Use the single immediate command instead of CORB/RIRB for simplicity
476 * Note: according to Intel, this is not preferred use. The command was
477 * intended for the BIOS only, and may get confused with unsolicited
478 * responses. So, we shouldn't use it for normal operation from the
480 * I left the codes, however, for debugging/testing purposes.
483 #define azx_alloc_cmd_io(chip) 0
484 #define azx_init_cmd_io(chip)
485 #define azx_free_cmd_io(chip)
488 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
489 unsigned int verb, unsigned int para)
491 azx_t *chip = codec->bus->private_data;
495 val = (u32)(codec->addr & 0x0f) << 28;
496 val |= (u32)direct << 27;
497 val |= (u32)nid << 20;
502 /* check ICB busy bit */
503 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
504 /* Clear IRV valid bit */
505 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
506 azx_writel(chip, IC, val);
507 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
512 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
516 /* receive a response */
517 static unsigned int azx_get_response(struct hda_codec *codec)
519 azx_t *chip = codec->bus->private_data;
523 /* check IRV busy bit */
524 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
525 return azx_readl(chip, IR);
528 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
529 return (unsigned int)-1;
532 #define azx_update_rirb(chip)
534 #endif /* USE_CORB_RIRB */
536 /* reset codec link */
537 static int azx_reset(azx_t *chip)
541 /* reset controller */
542 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
545 while (azx_readb(chip, GCTL) && --count)
548 /* delay for >= 100us for codec PLL to settle per spec
549 * Rev 0.9 section 5.5.1
553 /* Bring controller out of reset */
554 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
557 while (! azx_readb(chip, GCTL) && --count)
560 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
563 /* check to see if controller is ready */
564 if (! azx_readb(chip, GCTL)) {
565 snd_printd("azx_reset: controller not ready!\n");
569 /* Accept unsolicited responses */
570 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
573 if (! chip->codec_mask) {
574 chip->codec_mask = azx_readw(chip, STATESTS);
575 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
586 /* enable interrupts */
587 static void azx_int_enable(azx_t *chip)
589 /* enable controller CIE and GIE */
590 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
591 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
594 /* disable interrupts */
595 static void azx_int_disable(azx_t *chip)
599 /* disable interrupts in stream descriptor */
600 for (i = 0; i < MAX_ICH6_DEV; i++) {
601 azx_dev_t *azx_dev = &chip->azx_dev[i];
602 azx_sd_writeb(azx_dev, SD_CTL,
603 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
606 /* disable SIE for all streams */
607 azx_writeb(chip, INTCTL, 0);
609 /* disable controller CIE and GIE */
610 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
611 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
614 /* clear interrupts */
615 static void azx_int_clear(azx_t *chip)
619 /* clear stream status */
620 for (i = 0; i < MAX_ICH6_DEV; i++) {
621 azx_dev_t *azx_dev = &chip->azx_dev[i];
622 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
626 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
628 /* clear rirb status */
629 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
631 /* clear int status */
632 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
636 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
639 azx_writeb(chip, INTCTL,
640 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
641 /* set DMA start and interrupt mask */
642 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
643 SD_CTL_DMA_START | SD_INT_MASK);
647 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
650 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
651 ~(SD_CTL_DMA_START | SD_INT_MASK));
652 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
654 azx_writeb(chip, INTCTL,
655 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
660 * initialize the chip
662 static void azx_init_chip(azx_t *chip)
664 unsigned char tcsel_reg, ati_misc_cntl2;
666 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
667 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
668 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
670 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
671 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
673 /* reset controller */
676 /* initialize interrupts */
678 azx_int_enable(chip);
680 /* initialize the codec command I/O */
681 azx_init_cmd_io(chip);
683 if (chip->position_fix == POS_FIX_POSBUF) {
684 /* program the position buffer */
685 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
686 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
689 /* For ATI SB450 azalia HD audio, we need to enable snoop */
690 if (chip->pci->vendor == PCI_VENDOR_ID_ATI &&
691 chip->pci->device == ATI_SB450_HDAUDIO_PCI_DEVICE_ID) {
692 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
694 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
695 (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
703 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
705 azx_t *chip = dev_id;
710 spin_lock(&chip->reg_lock);
712 status = azx_readl(chip, INTSTS);
714 spin_unlock(&chip->reg_lock);
718 for (i = 0; i < MAX_ICH6_DEV; i++) {
719 azx_dev = &chip->azx_dev[i];
720 if (status & azx_dev->sd_int_sta_mask) {
721 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
722 if (azx_dev->substream && azx_dev->running) {
723 spin_unlock(&chip->reg_lock);
724 snd_pcm_period_elapsed(azx_dev->substream);
725 spin_lock(&chip->reg_lock);
731 status = azx_readb(chip, RIRBSTS);
732 if (status & RIRB_INT_MASK) {
733 if (status & RIRB_INT_RESPONSE)
734 azx_update_rirb(chip);
735 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
739 /* clear state status int */
740 if (azx_readb(chip, STATESTS) & 0x04)
741 azx_writeb(chip, STATESTS, 0x04);
743 spin_unlock(&chip->reg_lock);
752 static void azx_setup_periods(azx_dev_t *azx_dev)
754 u32 *bdl = azx_dev->bdl;
755 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
758 /* reset BDL address */
759 azx_sd_writel(azx_dev, SD_BDLPL, 0);
760 azx_sd_writel(azx_dev, SD_BDLPU, 0);
762 /* program the initial BDL entries */
763 for (idx = 0; idx < azx_dev->frags; idx++) {
764 unsigned int off = idx << 2; /* 4 dword step */
765 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
766 /* program the address field of the BDL entry */
767 bdl[off] = cpu_to_le32((u32)addr);
768 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
770 /* program the size field of the BDL entry */
771 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
773 /* program the IOC to enable interrupt when buffer completes */
774 bdl[off+3] = cpu_to_le32(0x01);
779 * set up the SD for streaming
781 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
786 /* make sure the run bit is zero for SD */
787 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
789 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
792 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
795 val &= ~SD_CTL_STREAM_RESET;
796 azx_sd_writeb(azx_dev, SD_CTL, val);
800 /* waiting for hardware to report that the stream is out of reset */
801 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
805 /* program the stream_tag */
806 azx_sd_writel(azx_dev, SD_CTL,
807 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
808 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
810 /* program the length of samples in cyclic buffer */
811 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
813 /* program the stream format */
814 /* this value needs to be the same as the one programmed */
815 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
817 /* program the stream LVI (last valid index) of the BDL */
818 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
820 /* program the BDL address */
821 /* lower BDL address */
822 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
823 /* upper BDL address */
824 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
826 if (chip->position_fix == POS_FIX_POSBUF) {
827 /* enable the position buffer */
828 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
829 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
832 /* set the interrupt enable bits in the descriptor control register */
833 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
840 * Codec initialization
843 static int __devinit azx_codec_create(azx_t *chip, const char *model)
845 struct hda_bus_template bus_temp;
848 memset(&bus_temp, 0, sizeof(bus_temp));
849 bus_temp.private_data = chip;
850 bus_temp.modelname = model;
851 bus_temp.pci = chip->pci;
852 bus_temp.ops.command = azx_send_cmd;
853 bus_temp.ops.get_response = azx_get_response;
855 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
859 for (c = 0; c < AZX_MAX_CODECS; c++) {
860 if (chip->codec_mask & (1 << c)) {
861 err = snd_hda_codec_new(chip->bus, c, NULL);
868 snd_printk(KERN_ERR SFX "no codecs initialized\n");
880 /* assign a stream for the PCM */
881 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
884 dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
885 for (i = 0; i < 4; i++, dev++)
886 if (! chip->azx_dev[dev].opened) {
887 chip->azx_dev[dev].opened = 1;
888 return &chip->azx_dev[dev];
893 /* release the assigned stream */
894 static inline void azx_release_device(azx_dev_t *azx_dev)
899 static snd_pcm_hardware_t azx_pcm_hw = {
900 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
901 SNDRV_PCM_INFO_BLOCK_TRANSFER |
902 SNDRV_PCM_INFO_MMAP_VALID |
903 SNDRV_PCM_INFO_PAUSE /*|*/
904 /*SNDRV_PCM_INFO_RESUME*/),
905 .formats = SNDRV_PCM_FMTBIT_S16_LE,
906 .rates = SNDRV_PCM_RATE_48000,
911 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
912 .period_bytes_min = 128,
913 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
915 .periods_max = AZX_MAX_FRAG,
921 struct hda_codec *codec;
922 struct hda_pcm_stream *hinfo[2];
925 static int azx_pcm_open(snd_pcm_substream_t *substream)
927 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
928 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
929 azx_t *chip = apcm->chip;
931 snd_pcm_runtime_t *runtime = substream->runtime;
935 down(&chip->open_mutex);
936 azx_dev = azx_assign_device(chip, substream->stream);
937 if (azx_dev == NULL) {
938 up(&chip->open_mutex);
941 runtime->hw = azx_pcm_hw;
942 runtime->hw.channels_min = hinfo->channels_min;
943 runtime->hw.channels_max = hinfo->channels_max;
944 runtime->hw.formats = hinfo->formats;
945 runtime->hw.rates = hinfo->rates;
946 snd_pcm_limit_hw_rates(runtime);
947 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
948 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
949 azx_release_device(azx_dev);
950 up(&chip->open_mutex);
953 spin_lock_irqsave(&chip->reg_lock, flags);
954 azx_dev->substream = substream;
955 azx_dev->running = 0;
956 spin_unlock_irqrestore(&chip->reg_lock, flags);
958 runtime->private_data = azx_dev;
959 up(&chip->open_mutex);
963 static int azx_pcm_close(snd_pcm_substream_t *substream)
965 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
966 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
967 azx_t *chip = apcm->chip;
968 azx_dev_t *azx_dev = get_azx_dev(substream);
971 down(&chip->open_mutex);
972 spin_lock_irqsave(&chip->reg_lock, flags);
973 azx_dev->substream = NULL;
974 azx_dev->running = 0;
975 spin_unlock_irqrestore(&chip->reg_lock, flags);
976 azx_release_device(azx_dev);
977 hinfo->ops.close(hinfo, apcm->codec, substream);
978 up(&chip->open_mutex);
982 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
984 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
987 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
989 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
990 azx_dev_t *azx_dev = get_azx_dev(substream);
991 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
993 /* reset BDL address */
994 azx_sd_writel(azx_dev, SD_BDLPL, 0);
995 azx_sd_writel(azx_dev, SD_BDLPU, 0);
996 azx_sd_writel(azx_dev, SD_CTL, 0);
998 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1000 return snd_pcm_lib_free_pages(substream);
1003 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
1005 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1006 azx_t *chip = apcm->chip;
1007 azx_dev_t *azx_dev = get_azx_dev(substream);
1008 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1009 snd_pcm_runtime_t *runtime = substream->runtime;
1011 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1012 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1013 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1014 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1018 if (! azx_dev->format_val) {
1019 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1020 runtime->rate, runtime->channels, runtime->format);
1024 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1025 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1026 azx_setup_periods(azx_dev);
1027 azx_setup_controller(chip, azx_dev);
1028 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1029 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1031 azx_dev->fifo_size = 0;
1033 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1034 azx_dev->format_val, substream);
1037 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1039 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1040 azx_dev_t *azx_dev = get_azx_dev(substream);
1041 azx_t *chip = apcm->chip;
1044 spin_lock(&chip->reg_lock);
1046 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1047 case SNDRV_PCM_TRIGGER_RESUME:
1048 case SNDRV_PCM_TRIGGER_START:
1049 azx_stream_start(chip, azx_dev);
1050 azx_dev->running = 1;
1052 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1053 case SNDRV_PCM_TRIGGER_SUSPEND:
1054 case SNDRV_PCM_TRIGGER_STOP:
1055 azx_stream_stop(chip, azx_dev);
1056 azx_dev->running = 0;
1061 spin_unlock(&chip->reg_lock);
1062 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1063 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1064 cmd == SNDRV_PCM_TRIGGER_STOP) {
1066 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1072 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1074 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1075 azx_t *chip = apcm->chip;
1076 azx_dev_t *azx_dev = get_azx_dev(substream);
1079 if (chip->position_fix == POS_FIX_POSBUF) {
1080 /* use the position buffer */
1081 pos = *azx_dev->posbuf;
1084 pos = azx_sd_readl(azx_dev, SD_LPIB);
1085 if (chip->position_fix == POS_FIX_FIFO)
1086 pos += azx_dev->fifo_size;
1088 if (pos >= azx_dev->bufsize)
1090 return bytes_to_frames(substream->runtime, pos);
1093 static snd_pcm_ops_t azx_pcm_ops = {
1094 .open = azx_pcm_open,
1095 .close = azx_pcm_close,
1096 .ioctl = snd_pcm_lib_ioctl,
1097 .hw_params = azx_pcm_hw_params,
1098 .hw_free = azx_pcm_hw_free,
1099 .prepare = azx_pcm_prepare,
1100 .trigger = azx_pcm_trigger,
1101 .pointer = azx_pcm_pointer,
1104 static void azx_pcm_free(snd_pcm_t *pcm)
1106 kfree(pcm->private_data);
1109 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1110 struct hda_pcm *cpcm, int pcm_dev)
1114 struct azx_pcm *apcm;
1116 snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1117 snd_assert(cpcm->name, return -EINVAL);
1119 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1120 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1124 strcpy(pcm->name, cpcm->name);
1125 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1129 apcm->codec = codec;
1130 apcm->hinfo[0] = &cpcm->stream[0];
1131 apcm->hinfo[1] = &cpcm->stream[1];
1132 pcm->private_data = apcm;
1133 pcm->private_free = azx_pcm_free;
1134 if (cpcm->stream[0].substreams)
1135 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1136 if (cpcm->stream[1].substreams)
1137 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1138 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1139 snd_dma_pci_data(chip->pci),
1140 1024 * 64, 1024 * 128);
1141 chip->pcm[pcm_dev] = pcm;
1142 chip->pcm_devs = pcm_dev + 1;
1147 static int __devinit azx_pcm_create(azx_t *chip)
1149 struct list_head *p;
1150 struct hda_codec *codec;
1154 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1158 list_for_each(p, &chip->bus->codec_list) {
1159 codec = list_entry(p, struct hda_codec, list);
1160 for (c = 0; c < codec->num_pcms; c++) {
1161 if (pcm_dev >= AZX_MAX_PCMS) {
1162 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1165 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1175 * mixer creation - all stuff is implemented in hda module
1177 static int __devinit azx_mixer_create(azx_t *chip)
1179 return snd_hda_build_controls(chip->bus);
1184 * initialize SD streams
1186 static int __devinit azx_init_stream(azx_t *chip)
1190 /* initialize each stream (aka device)
1191 * assign the starting bdl address to each stream (device) and initialize
1193 for (i = 0; i < MAX_ICH6_DEV; i++) {
1194 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1195 azx_dev_t *azx_dev = &chip->azx_dev[i];
1196 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1197 azx_dev->bdl_addr = chip->bdl.addr + off;
1198 if (chip->position_fix == POS_FIX_POSBUF)
1199 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1200 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1201 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1202 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1203 azx_dev->sd_int_sta_mask = 1 << i;
1204 /* stream tag: must be non-zero and unique */
1206 azx_dev->stream_tag = i + 1;
1217 static int azx_suspend(snd_card_t *card, pm_message_t state)
1219 azx_t *chip = card->pm_private_data;
1222 for (i = 0; i < chip->pcm_devs; i++)
1224 snd_pcm_suspend_all(chip->pcm[i]);
1225 snd_hda_suspend(chip->bus, state);
1226 azx_free_cmd_io(chip);
1227 pci_disable_device(chip->pci);
1231 static int azx_resume(snd_card_t *card)
1233 azx_t *chip = card->pm_private_data;
1235 pci_enable_device(chip->pci);
1236 pci_set_master(chip->pci);
1237 azx_init_chip(chip);
1238 snd_hda_resume(chip->bus);
1241 #endif /* CONFIG_PM */
1247 static int azx_free(azx_t *chip)
1249 if (chip->initialized) {
1252 for (i = 0; i < MAX_ICH6_DEV; i++)
1253 azx_stream_stop(chip, &chip->azx_dev[i]);
1255 /* disable interrupts */
1256 azx_int_disable(chip);
1257 azx_int_clear(chip);
1259 /* disable CORB/RIRB */
1260 azx_free_cmd_io(chip);
1262 /* disable position buffer */
1263 azx_writel(chip, DPLBASE, 0);
1264 azx_writel(chip, DPUBASE, 0);
1266 /* wait a little for interrupts to finish */
1269 iounmap(chip->remap_addr);
1273 free_irq(chip->irq, (void*)chip);
1276 snd_dma_free_pages(&chip->bdl);
1278 snd_dma_free_pages(&chip->rb);
1279 if (chip->posbuf.area)
1280 snd_dma_free_pages(&chip->posbuf);
1281 pci_release_regions(chip->pci);
1282 pci_disable_device(chip->pci);
1288 static int azx_dev_free(snd_device_t *device)
1290 return azx_free(device->device_data);
1296 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
1297 int posfix, azx_t **rchip)
1301 static snd_device_ops_t ops = {
1302 .dev_free = azx_dev_free,
1307 if ((err = pci_enable_device(pci)) < 0)
1310 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1313 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1314 pci_disable_device(pci);
1318 spin_lock_init(&chip->reg_lock);
1319 init_MUTEX(&chip->open_mutex);
1324 chip->position_fix = posfix;
1326 if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1328 pci_disable_device(pci);
1332 chip->addr = pci_resource_start(pci,0);
1333 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1334 if (chip->remap_addr == NULL) {
1335 snd_printk(KERN_ERR SFX "ioremap error\n");
1340 if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1341 "HDA Intel", (void*)chip)) {
1342 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1346 chip->irq = pci->irq;
1348 pci_set_master(pci);
1349 synchronize_irq(chip->irq);
1351 /* allocate memory for the BDL for each stream */
1352 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1353 PAGE_SIZE, &chip->bdl)) < 0) {
1354 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1357 if (chip->position_fix == POS_FIX_POSBUF) {
1358 /* allocate memory for the position buffer */
1359 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1360 MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
1361 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1365 /* allocate CORB/RIRB */
1366 if ((err = azx_alloc_cmd_io(chip)) < 0)
1369 /* initialize streams */
1370 azx_init_stream(chip);
1372 /* initialize chip */
1373 azx_init_chip(chip);
1375 chip->initialized = 1;
1377 /* codec detection */
1378 if (! chip->codec_mask) {
1379 snd_printk(KERN_ERR SFX "no codecs found!\n");
1384 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1385 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1397 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1404 if (dev >= SNDRV_CARDS)
1406 if (! enable[dev]) {
1411 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1413 snd_printk(KERN_ERR SFX "Error creating card!\n");
1417 if ((err = azx_create(card, pci, position_fix[dev], &chip)) < 0) {
1418 snd_card_free(card);
1422 strcpy(card->driver, "HDA-Intel");
1423 strcpy(card->shortname, "HDA Intel");
1424 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1426 /* create codec instances */
1427 if ((err = azx_codec_create(chip, model[dev])) < 0) {
1428 snd_card_free(card);
1432 /* create PCM streams */
1433 if ((err = azx_pcm_create(chip)) < 0) {
1434 snd_card_free(card);
1438 /* create mixer controls */
1439 if ((err = azx_mixer_create(chip)) < 0) {
1440 snd_card_free(card);
1444 snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1445 snd_card_set_dev(card, &pci->dev);
1447 if ((err = snd_card_register(card)) < 0) {
1448 snd_card_free(card);
1452 pci_set_drvdata(pci, card);
1458 static void __devexit azx_remove(struct pci_dev *pci)
1460 snd_card_free(pci_get_drvdata(pci));
1461 pci_set_drvdata(pci, NULL);
1465 static struct pci_device_id azx_ids[] = {
1466 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
1467 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
1468 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
1469 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ATI SB450 */
1470 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* VIA VT8251/VT8237A */
1471 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SIS966 */
1472 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ALI 5461? */
1475 MODULE_DEVICE_TABLE(pci, azx_ids);
1477 /* pci_driver definition */
1478 static struct pci_driver driver = {
1479 .name = "HDA Intel",
1480 .id_table = azx_ids,
1482 .remove = __devexit_p(azx_remove),
1483 SND_PCI_PM_CALLBACKS
1486 static int __init alsa_card_azx_init(void)
1488 return pci_register_driver(&driver);
1491 static void __exit alsa_card_azx_exit(void)
1493 pci_unregister_driver(&driver);
1496 module_init(alsa_card_azx_init)
1497 module_exit(alsa_card_azx_exit)