err.no Git - linux-2.6/blob - sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 /* Power-Management-Code ( CONFIG_PM )
  23  * for ens1371 only ( FIXME )
  24  * derived from cs4281.c, atiixp.c and via82xx.c
  25  * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
  26  * by Kurt J. Bosch
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/gameport.h>
  37 #include <linux/moduleparam.h>
  38 #include <sound/core.h>
  39 #include <sound/control.h>
  40 #include <sound/pcm.h>
  41 #include <sound/rawmidi.h>
  42 #ifdef CHIP1371
  43 #include <sound/ac97_codec.h>
  44 #else
  45 #include <sound/ak4531_codec.h>
  46 #endif
  47 #include <sound/initval.h>
  48 #include <sound/asoundef.h>
  49
  50 #ifndef CHIP1371
  51 #undef CHIP1370
  52 #define CHIP1370
  53 #endif
  54
  55 #ifdef CHIP1370
  56 #define DRIVER_NAME "ENS1370"
  57 #else
  58 #define DRIVER_NAME "ENS1371"
  59 #endif
  60
  61
  62 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  63 MODULE_LICENSE("GPL");
  64 #ifdef CHIP1370
  65 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  66 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  67                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  68 #endif
  69 #ifdef CHIP1371
  70 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  71 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  72                 "{Ensoniq,AudioPCI ES1373},"
  73                 "{Creative Labs,Ectiva EV1938},"
  74                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  75                 "{Creative Labs,Vibra PCI128},"
  76                 "{Ectiva,EV1938}}");
  77 #endif
  78
  79 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  80 #define SUPPORT_JOYSTICK
  81 #endif
  82
  83 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  84 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  85 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  86 #ifdef SUPPORT_JOYSTICK
  87 #ifdef CHIP1371
  88 static int joystick_port[SNDRV_CARDS];
  89 static int spdif[SNDRV_CARDS];
  90 static int lineio[SNDRV_CARDS];
  91 #else
  92 static int joystick[SNDRV_CARDS];
  93 #endif
  94 #endif
  95
  96 module_param_array(index, int, NULL, 0444);
  97 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
  98 module_param_array(id, charp, NULL, 0444);
  99 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
 100 module_param_array(enable, bool, NULL, 0444);
 101 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
 102 #ifdef SUPPORT_JOYSTICK
 103 #ifdef CHIP1371
 104 module_param_array(joystick_port, int, NULL, 0444);
 105 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 106 module_param_array(spdif, int, NULL, 0444);
 107 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
 108 module_param_array(lineio, int, NULL, 0444);
 109 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
 110 #else
 111 module_param_array(joystick, bool, NULL, 0444);
 112 MODULE_PARM_DESC(joystick, "Enable joystick.");
 113 #endif
 114 #endif /* SUPPORT_JOYSTICK */
 115
 116 /* ES1371 chip ID */
 117 /* This is a little confusing because all ES1371 compatible chips have the
 118    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 119    This is only significant if you want to enable features on the later parts.
 120    Yes, I know it's stupid and why didn't we use the sub IDs?
 121 */
 122 #define ES1371REV_ES1373_A  0x04
 123 #define ES1371REV_ES1373_B  0x06
 124 #define ES1371REV_CT5880_A  0x07
 125 #define CT5880REV_CT5880_C  0x02
 126 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 127 #define CT5880REV_CT5880_E  0x04        /* mw */
 128 #define ES1371REV_ES1371_B  0x09
 129 #define EV1938REV_EV1938_A  0x00
 130 #define ES1371REV_ES1373_8  0x08
 131
 132 /*
 133  * Direct registers
 134  */
 135
 136 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 137
 138 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 139 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 140 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 141 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 142 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 143 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 144 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 145 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 146 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 147 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 148 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 149 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 150 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 151 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 152 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 153 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 154 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 155 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 156 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 157 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 158 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 159 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 160 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 161 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 162 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 163 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 164 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 165 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 166 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 167 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 168 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 169 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 170 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 171 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 172 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 173 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 174 #define   ES_UART_EN            (1<<3)          /* UART enable */
 175 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 176 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 177 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 178 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 179 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 180 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 181 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 182 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 183 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 184 #define   ES_1373_REAR_BIT26    (1<<26)
 185 #define   ES_1373_REAR_BIT24    (1<<24)
 186 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 187 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 188 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 189 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 190 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 191 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 192 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 193 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 194 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 195 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 196 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 197 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 198 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 199 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 200 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 201 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 202 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 203 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 204 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 205 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 206 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 207 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 208 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 209 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 210 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 211 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 212 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 213 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 214 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 215 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 216 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 217 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 218 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 219 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 220 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 221 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 222 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 223 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 224 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 225 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 226 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 227 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 228 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 229 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 230 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 231
 232 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 233 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 234 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 235 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 236 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 237 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 238 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 239 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 240 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 241 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 242 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 243 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 244 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 245
 246 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 247 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 248 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 249 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 250 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 251 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 252 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 253 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 254 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 255 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 256 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 257 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 258 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 259 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 260 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 261 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 262 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 263 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 264 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 265 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 266 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 267 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 268 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 269
 270 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 271
 272 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 273 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 274 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 275 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 276 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 277 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 278 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 279 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 280 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 281 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 282 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 283 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 284 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 285 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 286 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 287 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 288 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 289 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 290 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 291 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 292 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 293 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 294 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 295 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 296 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 297 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 298 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 299
 300 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 301 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 302 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 303 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 304 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 305 #define   ES_REG_COUNTM         (0xffff<<0)
 306 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 307
 308 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 309 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 310 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 311 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 312 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 313 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 314 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 315 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 316 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 317 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 318 #define   ES_REG_FSIZEM          (0xffff<<0)
 319 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 320 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 321 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 322
 323 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 324 #define   ES_REG_UF_VALID        (1<<8)
 325 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 326 #define   ES_REG_UF_BYTEM        (0xff<<0)
 327 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 328
 329
 330 /*
 331  *  Pages
 332  */
 333
 334 #define ES_PAGE_DAC     0x0c
 335 #define ES_PAGE_ADC     0x0d
 336 #define ES_PAGE_UART    0x0e
 337 #define ES_PAGE_UART1   0x0f
 338
 339 /*
 340  *  Sample rate converter addresses
 341  */
 342
 343 #define ES_SMPREG_DAC1          0x70
 344 #define ES_SMPREG_DAC2          0x74
 345 #define ES_SMPREG_ADC           0x78
 346 #define ES_SMPREG_VOL_ADC       0x6c
 347 #define ES_SMPREG_VOL_DAC1      0x7c
 348 #define ES_SMPREG_VOL_DAC2      0x7e
 349 #define ES_SMPREG_TRUNC_N       0x00
 350 #define ES_SMPREG_INT_REGS      0x01
 351 #define ES_SMPREG_ACCUM_FRAC    0x02
 352 #define ES_SMPREG_VFREQ_FRAC    0x03
 353
 354 /*
 355  *  Some contants
 356  */
 357
 358 #define ES_1370_SRCLOCK    1411200
 359 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 360
 361 /*
 362  *  Open modes
 363  */
 364
 365 #define ES_MODE_PLAY1   0x0001
 366 #define ES_MODE_PLAY2   0x0002
 367 #define ES_MODE_CAPTURE 0x0004
 368
 369 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 370 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 371
 372 /*
 373
 374  */
 375
 376 struct ensoniq {
 377         spinlock_t reg_lock;
 378         struct semaphore src_mutex;
 379
 380         int irq;
 381
 382         unsigned long playback1size;
 383         unsigned long playback2size;
 384         unsigned long capture3size;
 385
 386         unsigned long port;
 387         unsigned int mode;
 388         unsigned int uartm;     /* UART mode */
 389
 390         unsigned int ctrl;      /* control register */
 391         unsigned int sctrl;     /* serial control register */
 392         unsigned int cssr;      /* control status register */
 393         unsigned int uartc;     /* uart control register */
 394         unsigned int rev;       /* chip revision */
 395
 396         union {
 397 #ifdef CHIP1371
 398                 struct {
 399                         struct snd_ac97 *ac97;
 400                 } es1371;
 401 #else
 402                 struct {
 403                         int pclkdiv_lock;
 404                         struct snd_ak4531 *ak4531;
 405                 } es1370;
 406 #endif
 407         } u;
 408
 409         struct pci_dev *pci;
 410         unsigned short subsystem_vendor_id;
 411         unsigned short subsystem_device_id;
 412         struct snd_card *card;
 413         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
 414         struct snd_pcm *pcm2;   /* DAC2 PCM */
 415         struct snd_pcm_substream *playback1_substream;
 416         struct snd_pcm_substream *playback2_substream;
 417         struct snd_pcm_substream *capture_substream;
 418         unsigned int p1_dma_size;
 419         unsigned int p2_dma_size;
 420         unsigned int c_dma_size;
 421         unsigned int p1_period_size;
 422         unsigned int p2_period_size;
 423         unsigned int c_period_size;
 424         struct snd_rawmidi *rmidi;
 425         struct snd_rawmidi_substream *midi_input;
 426         struct snd_rawmidi_substream *midi_output;
 427
 428         unsigned int spdif;
 429         unsigned int spdif_default;
 430         unsigned int spdif_stream;
 431
 432 #ifdef CHIP1370
 433         struct snd_dma_buffer dma_bug;
 434 #endif
 435
 436 #ifdef SUPPORT_JOYSTICK
 437         struct gameport *gameport;
 438 #endif
 439 };
 440
 441 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 442
 443 static struct pci_device_id snd_audiopci_ids[] = {
 444 #ifdef CHIP1370
 445         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 446 #endif
 447 #ifdef CHIP1371
 448         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 449         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 450         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 451 #endif
 452         { 0, }
 453 };
 454
 455 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 456
 457 /*
 458  *  constants
 459  */
 460
 461 #define POLL_COUNT      0xa000
 462
 463 #ifdef CHIP1370
 464 static unsigned int snd_es1370_fixed_rates[] =
 465         {5512, 11025, 22050, 44100};
 466 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
 467         .count = 4,
 468         .list = snd_es1370_fixed_rates,
 469         .mask = 0,
 470 };
 471 static struct snd_ratnum es1370_clock = {
 472         .num = ES_1370_SRCLOCK,
 473         .den_min = 29,
 474         .den_max = 353,
 475         .den_step = 1,
 476 };
 477 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
 478         .nrats = 1,
 479         .rats = &es1370_clock,
 480 };
 481 #else
 482 static struct snd_ratden es1371_dac_clock = {
 483         .num_min = 3000 * (1 << 15),
 484         .num_max = 48000 * (1 << 15),
 485         .num_step = 3000,
 486         .den = 1 << 15,
 487 };
 488 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
 489         .nrats = 1,
 490         .rats = &es1371_dac_clock,
 491 };
 492 static struct snd_ratnum es1371_adc_clock = {
 493         .num = 48000 << 15,
 494         .den_min = 32768,
 495         .den_max = 393216,
 496         .den_step = 1,
 497 };
 498 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
 499         .nrats = 1,
 500         .rats = &es1371_adc_clock,
 501 };
 502 #endif
 503 static const unsigned int snd_ensoniq_sample_shift[] =
 504         {0, 1, 1, 2};
 505
 506 /*
 507  *  common I/O routines
 508  */
 509
 510 #ifdef CHIP1371
 511
 512 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
 513 {
 514         unsigned int t, r = 0;
 515
 516         for (t = 0; t < POLL_COUNT; t++) {
 517                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 518                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 519                         return r;
 520                 cond_resched();
 521         }
 522         snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n",
 523                    ES_REG(ensoniq, 1371_SMPRATE), r);
 524         return 0;
 525 }
 526
 527 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
 528 {
 529         unsigned int temp, i, orig, r;
 530
 531         /* wait for ready */
 532         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 533
 534         /* expose the SRC state bits */
 535         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 536                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 537         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 538         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 539
 540         /* now, wait for busy and the correct time to read */
 541         temp = snd_es1371_wait_src_ready(ensoniq);
 542
 543         if ((temp & 0x00870000) != 0x00010000) {
 544                 /* wait for the right state */
 545                 for (i = 0; i < POLL_COUNT; i++) {
 546                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 547                         if ((temp & 0x00870000) == 0x00010000)
 548                                 break;
 549                 }
 550         }
 551
 552         /* hide the state bits */
 553         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 554                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 555         r |= ES_1371_SRC_RAM_ADDRO(reg);
 556         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 557
 558         return temp;
 559 }
 560
 561 static void snd_es1371_src_write(struct ensoniq * ensoniq,
 562                                  unsigned short reg, unsigned short data)
 563 {
 564         unsigned int r;
 565
 566         r = snd_es1371_wait_src_ready(ensoniq) &
 567             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 568              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 569         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 570         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 571 }
 572
 573 #endif /* CHIP1371 */
 574
 575 #ifdef CHIP1370
 576
 577 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
 578                                    unsigned short reg, unsigned short val)
 579 {
 580         struct ensoniq *ensoniq = ak4531->private_data;
 581         unsigned long end_time = jiffies + HZ / 10;
 582
 583 #if 0
 584         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
 585                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 586 #endif
 587         do {
 588                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 589                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 590                         return;
 591                 }
 592                 schedule_timeout_uninterruptible(1);
 593         } while (time_after(end_time, jiffies));
 594         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
 595                    inl(ES_REG(ensoniq, STATUS)));
 596 }
 597
 598 #endif /* CHIP1370 */
 599
 600 #ifdef CHIP1371
 601
 602 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
 603                                    unsigned short reg, unsigned short val)
 604 {
 605         struct ensoniq *ensoniq = ac97->private_data;
 606         unsigned int t, x;
 607
 608         down(&ensoniq->src_mutex);
 609         for (t = 0; t < POLL_COUNT; t++) {
 610                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 611                         /* save the current state for latter */
 612                         x = snd_es1371_wait_src_ready(ensoniq);
 613                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 614                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 615                              ES_REG(ensoniq, 1371_SMPRATE));
 616                         /* wait for not busy (state 0) first to avoid
 617                            transition states */
 618                         for (t = 0; t < POLL_COUNT; t++) {
 619                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 620                                     0x00000000)
 621                                         break;
 622                         }
 623                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 624                         for (t = 0; t < POLL_COUNT; t++) {
 625                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 626                                     0x00010000)
 627                                         break;
 628                         }
 629                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 630                         /* restore SRC reg */
 631                         snd_es1371_wait_src_ready(ensoniq);
 632                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 633                         up(&ensoniq->src_mutex);
 634                         return;
 635                 }
 636         }
 637         up(&ensoniq->src_mutex);
 638         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
 639                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 640 }
 641
 642 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
 643                                             unsigned short reg)
 644 {
 645         struct ensoniq *ensoniq = ac97->private_data;
 646         unsigned int t, x, fail = 0;
 647
 648       __again:
 649         down(&ensoniq->src_mutex);
 650         for (t = 0; t < POLL_COUNT; t++) {
 651                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 652                         /* save the current state for latter */
 653                         x = snd_es1371_wait_src_ready(ensoniq);
 654                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 655                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 656                              ES_REG(ensoniq, 1371_SMPRATE));
 657                         /* wait for not busy (state 0) first to avoid
 658                            transition states */
 659                         for (t = 0; t < POLL_COUNT; t++) {
 660                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 661                                     0x00000000)
 662                                         break;
 663                         }
 664                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 665                         for (t = 0; t < POLL_COUNT; t++) {
 666                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 667                                     0x00010000)
 668                                         break;
 669                         }
 670                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 671                         /* restore SRC reg */
 672                         snd_es1371_wait_src_ready(ensoniq);
 673                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 674                         /* wait for WIP again */
 675                         for (t = 0; t < POLL_COUNT; t++) {
 676                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 677                                         break;
 678                         }
 679                         /* now wait for the stinkin' data (RDY) */
 680                         for (t = 0; t < POLL_COUNT; t++) {
 681                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 682                                         up(&ensoniq->src_mutex);
 683                                         return ES_1371_CODEC_READ(x);
 684                                 }
 685                         }
 686                         up(&ensoniq->src_mutex);
 687                         if (++fail > 10) {
 688                                 snd_printk(KERN_ERR "codec read timeout (final) "
 689                                            "at 0x%lx, reg = 0x%x [0x%x]\n",
 690                                            ES_REG(ensoniq, 1371_CODEC), reg,
 691                                            inl(ES_REG(ensoniq, 1371_CODEC)));
 692                                 return 0;
 693                         }
 694                         goto __again;
 695                 }
 696         }
 697         up(&ensoniq->src_mutex);
 698         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
 699                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 700         return 0;
 701 }
 702
 703 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
 704 {
 705         msleep(750);
 706         snd_es1371_codec_read(ac97, AC97_RESET);
 707         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
 708         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
 709         msleep(50);
 710 }
 711
 712 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
 713 {
 714         unsigned int n, truncm, freq, result;
 715
 716         down(&ensoniq->src_mutex);
 717         n = rate / 3000;
 718         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 719                 n--;
 720         truncm = (21 * n - 1) | 1;
 721         freq = ((48000UL << 15) / rate) * n;
 722         result = (48000UL << 15) / (freq / n);
 723         if (rate >= 24000) {
 724                 if (truncm > 239)
 725                         truncm = 239;
 726                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 727                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 728         } else {
 729                 if (truncm > 119)
 730                         truncm = 119;
 731                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 732                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 733         }
 734         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 735                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
 736                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 737                              ((freq >> 5) & 0xfc00));
 738         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 739         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 740         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 741         up(&ensoniq->src_mutex);
 742 }
 743
 744 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
 745 {
 746         unsigned int freq, r;
 747
 748         down(&ensoniq->src_mutex);
 749         freq = ((rate << 15) + 1500) / 3000;
 750         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 751                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
 752                 ES_1371_DIS_P1;
 753         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 754         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 755                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
 756                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 757                              ((freq >> 5) & 0xfc00));
 758         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 759         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 760                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
 761         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 762         up(&ensoniq->src_mutex);
 763 }
 764
 765 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
 766 {
 767         unsigned int freq, r;
 768
 769         down(&ensoniq->src_mutex);
 770         freq = ((rate << 15) + 1500) / 3000;
 771         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 772                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
 773                 ES_1371_DIS_P2;
 774         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 775         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 776                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
 777                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 778                              ((freq >> 5) & 0xfc00));
 779         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
 780                              freq & 0x7fff);
 781         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 782                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
 783         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 784         up(&ensoniq->src_mutex);
 785 }
 786
 787 #endif /* CHIP1371 */
 788
 789 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
 790 {
 791         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 792         switch (cmd) {
 793         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 794         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 795         {
 796                 unsigned int what = 0;
 797                 struct list_head *pos;
 798                 struct snd_pcm_substream *s;
 799                 snd_pcm_group_for_each(pos, substream) {
 800                         s = snd_pcm_group_substream_entry(pos);
 801                         if (s == ensoniq->playback1_substream) {
 802                                 what |= ES_P1_PAUSE;
 803                                 snd_pcm_trigger_done(s, substream);
 804                         } else if (s == ensoniq->playback2_substream) {
 805                                 what |= ES_P2_PAUSE;
 806                                 snd_pcm_trigger_done(s, substream);
 807                         } else if (s == ensoniq->capture_substream)
 808                                 return -EINVAL;
 809                 }
 810                 spin_lock(&ensoniq->reg_lock);
 811                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 812                         ensoniq->sctrl |= what;
 813                 else
 814                         ensoniq->sctrl &= ~what;
 815                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 816                 spin_unlock(&ensoniq->reg_lock);
 817                 break;
 818         }
 819         case SNDRV_PCM_TRIGGER_START:
 820         case SNDRV_PCM_TRIGGER_STOP:
 821         {
 822                 unsigned int what = 0;
 823                 struct list_head *pos;
 824                 struct snd_pcm_substream *s;
 825                 snd_pcm_group_for_each(pos, substream) {
 826                         s = snd_pcm_group_substream_entry(pos);
 827                         if (s == ensoniq->playback1_substream) {
 828                                 what |= ES_DAC1_EN;
 829                                 snd_pcm_trigger_done(s, substream);
 830                         } else if (s == ensoniq->playback2_substream) {
 831                                 what |= ES_DAC2_EN;
 832                                 snd_pcm_trigger_done(s, substream);
 833                         } else if (s == ensoniq->capture_substream) {
 834                                 what |= ES_ADC_EN;
 835                                 snd_pcm_trigger_done(s, substream);
 836                         }
 837                 }
 838                 spin_lock(&ensoniq->reg_lock);
 839                 if (cmd == SNDRV_PCM_TRIGGER_START)
 840                         ensoniq->ctrl |= what;
 841                 else
 842                         ensoniq->ctrl &= ~what;
 843                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 844                 spin_unlock(&ensoniq->reg_lock);
 845                 break;
 846         }
 847         default:
 848                 return -EINVAL;
 849         }
 850         return 0;
 851 }
 852
 853 /*
 854  *  PCM part
 855  */
 856
 857 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
 858                                  struct snd_pcm_hw_params *hw_params)
 859 {
 860         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 861 }
 862
 863 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
 864 {
 865         return snd_pcm_lib_free_pages(substream);
 866 }
 867
 868 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
 869 {
 870         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 871         struct snd_pcm_runtime *runtime = substream->runtime;
 872         unsigned int mode = 0;
 873
 874         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 875         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 876         if (snd_pcm_format_width(runtime->format) == 16)
 877                 mode |= 0x02;
 878         if (runtime->channels > 1)
 879                 mode |= 0x01;
 880         spin_lock_irq(&ensoniq->reg_lock);
 881         ensoniq->ctrl &= ~ES_DAC1_EN;
 882 #ifdef CHIP1371
 883         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 884         if (runtime->rate == 48000)
 885                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 886         else
 887                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 888 #endif
 889         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 890         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 891         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 892         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 893         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 894         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 895         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 896         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 897              ES_REG(ensoniq, DAC1_COUNT));
 898 #ifdef CHIP1370
 899         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 900         switch (runtime->rate) {
 901         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 902         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 903         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 904         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 905         default: snd_BUG();
 906         }
 907 #endif
 908         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 909         spin_unlock_irq(&ensoniq->reg_lock);
 910 #ifndef CHIP1370
 911         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 912 #endif
 913         return 0;
 914 }
 915
 916 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
 917 {
 918         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 919         struct snd_pcm_runtime *runtime = substream->runtime;
 920         unsigned int mode = 0;
 921
 922         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 923         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 924         if (snd_pcm_format_width(runtime->format) == 16)
 925                 mode |= 0x02;
 926         if (runtime->channels > 1)
 927                 mode |= 0x01;
 928         spin_lock_irq(&ensoniq->reg_lock);
 929         ensoniq->ctrl &= ~ES_DAC2_EN;
 930         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 931         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 932         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 933         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 934         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 935                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 936         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 937                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 938         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 939         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 940              ES_REG(ensoniq, DAC2_COUNT));
 941 #ifdef CHIP1370
 942         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 943                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 944                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 945                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 946         }
 947 #endif
 948         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 949         spin_unlock_irq(&ensoniq->reg_lock);
 950 #ifndef CHIP1370
 951         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 952 #endif
 953         return 0;
 954 }
 955
 956 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
 957 {
 958         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 959         struct snd_pcm_runtime *runtime = substream->runtime;
 960         unsigned int mode = 0;
 961
 962         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 963         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 964         if (snd_pcm_format_width(runtime->format) == 16)
 965                 mode |= 0x02;
 966         if (runtime->channels > 1)
 967                 mode |= 0x01;
 968         spin_lock_irq(&ensoniq->reg_lock);
 969         ensoniq->ctrl &= ~ES_ADC_EN;
 970         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 971         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 972         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 973         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 974         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 975         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 976         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 977         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 978              ES_REG(ensoniq, ADC_COUNT));
 979 #ifdef CHIP1370
 980         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 981                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 982                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 983                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 984         }
 985 #endif
 986         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 987         spin_unlock_irq(&ensoniq->reg_lock);
 988 #ifndef CHIP1370
 989         snd_es1371_adc_rate(ensoniq, runtime->rate);
 990 #endif
 991         return 0;
 992 }
 993
 994 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
 995 {
 996         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 997         size_t ptr;
 998
 999         spin_lock(&ensoniq->reg_lock);
1000         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1001                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1002                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1003                 ptr = bytes_to_frames(substream->runtime, ptr);
1004         } else {
1005                 ptr = 0;
1006         }
1007         spin_unlock(&ensoniq->reg_lock);
1008         return ptr;
1009 }
1010
1011 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1012 {
1013         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1014         size_t ptr;
1015
1016         spin_lock(&ensoniq->reg_lock);
1017         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1018                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1019                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1020                 ptr = bytes_to_frames(substream->runtime, ptr);
1021         } else {
1022                 ptr = 0;
1023         }
1024         spin_unlock(&ensoniq->reg_lock);
1025         return ptr;
1026 }
1027
1028 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1029 {
1030         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1031         size_t ptr;
1032
1033         spin_lock(&ensoniq->reg_lock);
1034         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1035                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1036                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1037                 ptr = bytes_to_frames(substream->runtime, ptr);
1038         } else {
1039                 ptr = 0;
1040         }
1041         spin_unlock(&ensoniq->reg_lock);
1042         return ptr;
1043 }
1044
1045 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1046 {
1047         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1048                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1049                                  SNDRV_PCM_INFO_MMAP_VALID |
1050                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1051         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1052         .rates =
1053 #ifndef CHIP1370
1054                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1055 #else
1056                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1057                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1058                                  SNDRV_PCM_RATE_44100),
1059 #endif
1060         .rate_min =             4000,
1061         .rate_max =             48000,
1062         .channels_min =         1,
1063         .channels_max =         2,
1064         .buffer_bytes_max =     (128*1024),
1065         .period_bytes_min =     64,
1066         .period_bytes_max =     (128*1024),
1067         .periods_min =          1,
1068         .periods_max =          1024,
1069         .fifo_size =            0,
1070 };
1071
1072 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1073 {
1074         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1075                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1076                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1077                                  SNDRV_PCM_INFO_SYNC_START),
1078         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1079         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1080         .rate_min =             4000,
1081         .rate_max =             48000,
1082         .channels_min =         1,
1083         .channels_max =         2,
1084         .buffer_bytes_max =     (128*1024),
1085         .period_bytes_min =     64,
1086         .period_bytes_max =     (128*1024),
1087         .periods_min =          1,
1088         .periods_max =          1024,
1089         .fifo_size =            0,
1090 };
1091
1092 static struct snd_pcm_hardware snd_ensoniq_capture =
1093 {
1094         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1095                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1096                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1097         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1098         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1099         .rate_min =             4000,
1100         .rate_max =             48000,
1101         .channels_min =         1,
1102         .channels_max =         2,
1103         .buffer_bytes_max =     (128*1024),
1104         .period_bytes_min =     64,
1105         .period_bytes_max =     (128*1024),
1106         .periods_min =          1,
1107         .periods_max =          1024,
1108         .fifo_size =            0,
1109 };
1110
1111 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1112 {
1113         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1114         struct snd_pcm_runtime *runtime = substream->runtime;
1115
1116         ensoniq->mode |= ES_MODE_PLAY1;
1117         ensoniq->playback1_substream = substream;
1118         runtime->hw = snd_ensoniq_playback1;
1119         snd_pcm_set_sync(substream);
1120         spin_lock_irq(&ensoniq->reg_lock);
1121         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1122                 ensoniq->spdif_stream = ensoniq->spdif_default;
1123         spin_unlock_irq(&ensoniq->reg_lock);
1124 #ifdef CHIP1370
1125         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1126                                    &snd_es1370_hw_constraints_rates);
1127 #else
1128         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1129                                       &snd_es1371_hw_constraints_dac_clock);
1130 #endif
1131         return 0;
1132 }
1133
1134 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1135 {
1136         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1137         struct snd_pcm_runtime *runtime = substream->runtime;
1138
1139         ensoniq->mode |= ES_MODE_PLAY2;
1140         ensoniq->playback2_substream = substream;
1141         runtime->hw = snd_ensoniq_playback2;
1142         snd_pcm_set_sync(substream);
1143         spin_lock_irq(&ensoniq->reg_lock);
1144         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1145                 ensoniq->spdif_stream = ensoniq->spdif_default;
1146         spin_unlock_irq(&ensoniq->reg_lock);
1147 #ifdef CHIP1370
1148         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1149                                       &snd_es1370_hw_constraints_clock);
1150 #else
1151         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1152                                       &snd_es1371_hw_constraints_dac_clock);
1153 #endif
1154         return 0;
1155 }
1156
1157 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1158 {
1159         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1160         struct snd_pcm_runtime *runtime = substream->runtime;
1161
1162         ensoniq->mode |= ES_MODE_CAPTURE;
1163         ensoniq->capture_substream = substream;
1164         runtime->hw = snd_ensoniq_capture;
1165         snd_pcm_set_sync(substream);
1166 #ifdef CHIP1370
1167         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1168                                       &snd_es1370_hw_constraints_clock);
1169 #else
1170         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1171                                       &snd_es1371_hw_constraints_adc_clock);
1172 #endif
1173         return 0;
1174 }
1175
1176 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1177 {
1178         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1179
1180         ensoniq->playback1_substream = NULL;
1181         ensoniq->mode &= ~ES_MODE_PLAY1;
1182         return 0;
1183 }
1184
1185 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1186 {
1187         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1188
1189         ensoniq->playback2_substream = NULL;
1190         spin_lock_irq(&ensoniq->reg_lock);
1191 #ifdef CHIP1370
1192         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1193 #endif
1194         ensoniq->mode &= ~ES_MODE_PLAY2;
1195         spin_unlock_irq(&ensoniq->reg_lock);
1196         return 0;
1197 }
1198
1199 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1200 {
1201         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1202
1203         ensoniq->capture_substream = NULL;
1204         spin_lock_irq(&ensoniq->reg_lock);
1205 #ifdef CHIP1370
1206         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1207 #endif
1208         ensoniq->mode &= ~ES_MODE_CAPTURE;
1209         spin_unlock_irq(&ensoniq->reg_lock);
1210         return 0;
1211 }
1212
1213 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1214         .open =         snd_ensoniq_playback1_open,
1215         .close =        snd_ensoniq_playback1_close,
1216         .ioctl =        snd_pcm_lib_ioctl,
1217         .hw_params =    snd_ensoniq_hw_params,
1218         .hw_free =      snd_ensoniq_hw_free,
1219         .prepare =      snd_ensoniq_playback1_prepare,
1220         .trigger =      snd_ensoniq_trigger,
1221         .pointer =      snd_ensoniq_playback1_pointer,
1222 };
1223
1224 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1225         .open =         snd_ensoniq_playback2_open,
1226         .close =        snd_ensoniq_playback2_close,
1227         .ioctl =        snd_pcm_lib_ioctl,
1228         .hw_params =    snd_ensoniq_hw_params,
1229         .hw_free =      snd_ensoniq_hw_free,
1230         .prepare =      snd_ensoniq_playback2_prepare,
1231         .trigger =      snd_ensoniq_trigger,
1232         .pointer =      snd_ensoniq_playback2_pointer,
1233 };
1234
1235 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1236         .open =         snd_ensoniq_capture_open,
1237         .close =        snd_ensoniq_capture_close,
1238         .ioctl =        snd_pcm_lib_ioctl,
1239         .hw_params =    snd_ensoniq_hw_params,
1240         .hw_free =      snd_ensoniq_hw_free,
1241         .prepare =      snd_ensoniq_capture_prepare,
1242         .trigger =      snd_ensoniq_trigger,
1243         .pointer =      snd_ensoniq_capture_pointer,
1244 };
1245
1246 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1247                                      struct snd_pcm ** rpcm)
1248 {
1249         struct snd_pcm *pcm;
1250         int err;
1251
1252         if (rpcm)
1253                 *rpcm = NULL;
1254 #ifdef CHIP1370
1255         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1256 #else
1257         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1258 #endif
1259         if (err < 0)
1260                 return err;
1261
1262 #ifdef CHIP1370
1263         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1264 #else
1265         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1266 #endif
1267         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1268
1269         pcm->private_data = ensoniq;
1270         pcm->info_flags = 0;
1271 #ifdef CHIP1370
1272         strcpy(pcm->name, "ES1370 DAC2/ADC");
1273 #else
1274         strcpy(pcm->name, "ES1371 DAC2/ADC");
1275 #endif
1276         ensoniq->pcm1 = pcm;
1277
1278         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1279                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1280
1281         if (rpcm)
1282                 *rpcm = pcm;
1283         return 0;
1284 }
1285
1286 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1287                                       struct snd_pcm ** rpcm)
1288 {
1289         struct snd_pcm *pcm;
1290         int err;
1291
1292         if (rpcm)
1293                 *rpcm = NULL;
1294 #ifdef CHIP1370
1295         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1296 #else
1297         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1298 #endif
1299         if (err < 0)
1300                 return err;
1301
1302 #ifdef CHIP1370
1303         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1304 #else
1305         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1306 #endif
1307         pcm->private_data = ensoniq;
1308         pcm->info_flags = 0;
1309 #ifdef CHIP1370
1310         strcpy(pcm->name, "ES1370 DAC1");
1311 #else
1312         strcpy(pcm->name, "ES1371 DAC1");
1313 #endif
1314         ensoniq->pcm2 = pcm;
1315
1316         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1317                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1318
1319         if (rpcm)
1320                 *rpcm = pcm;
1321         return 0;
1322 }
1323
1324 /*
1325  *  Mixer section
1326  */
1327
1328 /*
1329  * ENS1371 mixer (including SPDIF interface)
1330  */
1331 #ifdef CHIP1371
1332 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1333                                   struct snd_ctl_elem_info *uinfo)
1334 {
1335         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1336         uinfo->count = 1;
1337         return 0;
1338 }
1339
1340 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1341                                          struct snd_ctl_elem_value *ucontrol)
1342 {
1343         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1344         spin_lock_irq(&ensoniq->reg_lock);
1345         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1346         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1347         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1348         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1349         spin_unlock_irq(&ensoniq->reg_lock);
1350         return 0;
1351 }
1352
1353 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1354                                          struct snd_ctl_elem_value *ucontrol)
1355 {
1356         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1357         unsigned int val;
1358         int change;
1359
1360         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1361               ((u32)ucontrol->value.iec958.status[1] << 8) |
1362               ((u32)ucontrol->value.iec958.status[2] << 16) |
1363               ((u32)ucontrol->value.iec958.status[3] << 24);
1364         spin_lock_irq(&ensoniq->reg_lock);
1365         change = ensoniq->spdif_default != val;
1366         ensoniq->spdif_default = val;
1367         if (change && ensoniq->playback1_substream == NULL &&
1368             ensoniq->playback2_substream == NULL)
1369                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1370         spin_unlock_irq(&ensoniq->reg_lock);
1371         return change;
1372 }
1373
1374 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1375                                       struct snd_ctl_elem_value *ucontrol)
1376 {
1377         ucontrol->value.iec958.status[0] = 0xff;
1378         ucontrol->value.iec958.status[1] = 0xff;
1379         ucontrol->value.iec958.status[2] = 0xff;
1380         ucontrol->value.iec958.status[3] = 0xff;
1381         return 0;
1382 }
1383
1384 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1385                                         struct snd_ctl_elem_value *ucontrol)
1386 {
1387         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1388         spin_lock_irq(&ensoniq->reg_lock);
1389         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1390         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1391         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1392         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1393         spin_unlock_irq(&ensoniq->reg_lock);
1394         return 0;
1395 }
1396
1397 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1398                                         struct snd_ctl_elem_value *ucontrol)
1399 {
1400         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1401         unsigned int val;
1402         int change;
1403
1404         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1405               ((u32)ucontrol->value.iec958.status[1] << 8) |
1406               ((u32)ucontrol->value.iec958.status[2] << 16) |
1407               ((u32)ucontrol->value.iec958.status[3] << 24);
1408         spin_lock_irq(&ensoniq->reg_lock);
1409         change = ensoniq->spdif_stream != val;
1410         ensoniq->spdif_stream = val;
1411         if (change && (ensoniq->playback1_substream != NULL ||
1412                        ensoniq->playback2_substream != NULL))
1413                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1414         spin_unlock_irq(&ensoniq->reg_lock);
1415         return change;
1416 }
1417
1418 #define ES1371_SPDIF(xname) \
1419 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1420   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1421
1422 static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol,
1423                                  struct snd_ctl_elem_info *uinfo)
1424 {
1425         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1426         uinfo->count = 1;
1427         uinfo->value.integer.min = 0;
1428         uinfo->value.integer.max = 1;
1429         return 0;
1430 }
1431
1432 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1433                                 struct snd_ctl_elem_value *ucontrol)
1434 {
1435         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1436
1437         spin_lock_irq(&ensoniq->reg_lock);
1438         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1439         spin_unlock_irq(&ensoniq->reg_lock);
1440         return 0;
1441 }
1442
1443 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1444                                 struct snd_ctl_elem_value *ucontrol)
1445 {
1446         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1447         unsigned int nval1, nval2;
1448         int change;
1449
1450         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1451         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1452         spin_lock_irq(&ensoniq->reg_lock);
1453         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1454         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1455         ensoniq->ctrl |= nval1;
1456         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1457         ensoniq->cssr |= nval2;
1458         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1459         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1460         spin_unlock_irq(&ensoniq->reg_lock);
1461         return change;
1462 }
1463
1464
1465 /* spdif controls */
1466 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1467         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1468         {
1469                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1470                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1471                 .info =         snd_ens1373_spdif_info,
1472                 .get =          snd_ens1373_spdif_default_get,
1473                 .put =          snd_ens1373_spdif_default_put,
1474         },
1475         {
1476                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1477                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1478                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1479                 .info =         snd_ens1373_spdif_info,
1480                 .get =          snd_ens1373_spdif_mask_get
1481         },
1482         {
1483                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1484                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1485                 .info =         snd_ens1373_spdif_info,
1486                 .get =          snd_ens1373_spdif_stream_get,
1487                 .put =          snd_ens1373_spdif_stream_put
1488         },
1489 };
1490
1491
1492 static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol,
1493                                 struct snd_ctl_elem_info *uinfo)
1494 {
1495         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1496         uinfo->count = 1;
1497         uinfo->value.integer.min = 0;
1498         uinfo->value.integer.max = 1;
1499         return 0;
1500 }
1501
1502 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1503                                struct snd_ctl_elem_value *ucontrol)
1504 {
1505         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1506         int val = 0;
1507
1508         spin_lock_irq(&ensoniq->reg_lock);
1509         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1510                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1511                 val = 1;
1512         ucontrol->value.integer.value[0] = val;
1513         spin_unlock_irq(&ensoniq->reg_lock);
1514         return 0;
1515 }
1516
1517 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1518                                struct snd_ctl_elem_value *ucontrol)
1519 {
1520         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1521         unsigned int nval1;
1522         int change;
1523
1524         nval1 = ucontrol->value.integer.value[0] ?
1525                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1526         spin_lock_irq(&ensoniq->reg_lock);
1527         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1528                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1529         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1530         ensoniq->cssr |= nval1;
1531         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1532         spin_unlock_irq(&ensoniq->reg_lock);
1533         return change;
1534 }
1535
1536 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1537 {
1538         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1539         .name =         "AC97 2ch->4ch Copy Switch",
1540         .info =         snd_es1373_rear_info,
1541         .get =          snd_es1373_rear_get,
1542         .put =          snd_es1373_rear_put,
1543 };
1544
1545 static int snd_es1373_line_info(struct snd_kcontrol *kcontrol,
1546                                 struct snd_ctl_elem_info *uinfo)
1547 {
1548         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1549         uinfo->count = 1;
1550         uinfo->value.integer.min = 0;
1551         uinfo->value.integer.max = 1;
1552         return 0;
1553 }
1554
1555 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1556                                struct snd_ctl_elem_value *ucontrol)
1557 {
1558         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1559         int val = 0;
1560
1561         spin_lock_irq(&ensoniq->reg_lock);
1562         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1563                 val = 1;
1564         ucontrol->value.integer.value[0] = val;
1565         spin_unlock_irq(&ensoniq->reg_lock);
1566         return 0;
1567 }
1568
1569 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1570                                struct snd_ctl_elem_value *ucontrol)
1571 {
1572         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1573         int changed;
1574         unsigned int ctrl;
1575
1576         spin_lock_irq(&ensoniq->reg_lock);
1577         ctrl = ensoniq->ctrl;
1578         if (ucontrol->value.integer.value[0])
1579                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1580         else
1581                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1582         changed = (ctrl != ensoniq->ctrl);
1583         if (changed)
1584                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1585         spin_unlock_irq(&ensoniq->reg_lock);
1586         return changed;
1587 }
1588
1589 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1590 {
1591         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1592         .name =         "Line In->Rear Out Switch",
1593         .info =         snd_es1373_line_info,
1594         .get =          snd_es1373_line_get,
1595         .put =          snd_es1373_line_put,
1596 };
1597
1598 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1599 {
1600         struct ensoniq *ensoniq = ac97->private_data;
1601         ensoniq->u.es1371.ac97 = NULL;
1602 }
1603
1604 static struct {
1605         unsigned short vid;             /* vendor ID */
1606         unsigned short did;             /* device ID */
1607         unsigned char rev;              /* revision */
1608 } es1371_spdif_present[] __devinitdata = {
1609         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1610         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1611         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1612         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1613         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1614         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1615 };
1616
1617 static int snd_ensoniq_1371_mixer(struct ensoniq * ensoniq, int has_spdif, int has_line)
1618 {
1619         struct snd_card *card = ensoniq->card;
1620         struct snd_ac97_bus *pbus;
1621         struct snd_ac97_template ac97;
1622         int err, idx;
1623         static struct snd_ac97_bus_ops ops = {
1624                 .write = snd_es1371_codec_write,
1625                 .read = snd_es1371_codec_read,
1626                 .wait = snd_es1371_codec_wait,
1627         };
1628
1629         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1630                 return err;
1631
1632         memset(&ac97, 0, sizeof(ac97));
1633         ac97.private_data = ensoniq;
1634         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1635         ac97.scaps = AC97_SCAP_AUDIO;
1636         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1637                 return err;
1638         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1639                 if ((ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1640                      ensoniq->pci->device == es1371_spdif_present[idx].did &&
1641                      ensoniq->rev == es1371_spdif_present[idx].rev) || has_spdif > 0) {
1642                         struct snd_kcontrol *kctl;
1643                         int i, index = 0;
1644
1645                         if (has_spdif < 0)
1646                                 break;
1647
1648                         ensoniq->spdif_default = ensoniq->spdif_stream =
1649                                 SNDRV_PCM_DEFAULT_CON_SPDIF;
1650                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1651
1652                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1653                                 index++;
1654
1655                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1656                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1657                                 if (! kctl)
1658                                         return -ENOMEM;
1659                                 kctl->id.index = index;
1660                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1661                                         return err;
1662                         }
1663                         break;
1664                 }
1665         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1666                 /* mirror rear to front speakers */
1667                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1668                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1669                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1670                 if (err < 0)
1671                         return err;
1672         }
1673         if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1674             (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1675             ((ensoniq->subsystem_vendor_id == 0x1458) &&
1676             (ensoniq->subsystem_device_id == 0xa000)) || /* GA-8IEXP */
1677             has_line > 0) {
1678                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1679                  if (err < 0)
1680                          return err;
1681         }
1682
1683         return 0;
1684 }
1685
1686 #endif /* CHIP1371 */
1687
1688 /* generic control callbacks for ens1370 */
1689 #ifdef CHIP1370
1690 #define ENSONIQ_CONTROL(xname, mask) \
1691 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1692   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1693   .private_value = mask }
1694
1695 static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol,
1696                                     struct snd_ctl_elem_info *uinfo)
1697 {
1698         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1699         uinfo->count = 1;
1700         uinfo->value.integer.min = 0;
1701         uinfo->value.integer.max = 1;
1702         return 0;
1703 }
1704
1705 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1706                                    struct snd_ctl_elem_value *ucontrol)
1707 {
1708         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1709         int mask = kcontrol->private_value;
1710
1711         spin_lock_irq(&ensoniq->reg_lock);
1712         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1713         spin_unlock_irq(&ensoniq->reg_lock);
1714         return 0;
1715 }
1716
1717 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1718                                    struct snd_ctl_elem_value *ucontrol)
1719 {
1720         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1721         int mask = kcontrol->private_value;
1722         unsigned int nval;
1723         int change;
1724
1725         nval = ucontrol->value.integer.value[0] ? mask : 0;
1726         spin_lock_irq(&ensoniq->reg_lock);
1727         change = (ensoniq->ctrl & mask) != nval;
1728         ensoniq->ctrl &= ~mask;
1729         ensoniq->ctrl |= nval;
1730         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1731         spin_unlock_irq(&ensoniq->reg_lock);
1732         return change;
1733 }
1734
1735 /*
1736  * ENS1370 mixer
1737  */
1738
1739 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1740 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1741 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1742 };
1743
1744 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1745
1746 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1747 {
1748         struct ensoniq *ensoniq = ak4531->private_data;
1749         ensoniq->u.es1370.ak4531 = NULL;
1750 }
1751
1752 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1753 {
1754         struct snd_card *card = ensoniq->card;
1755         struct snd_ak4531 ak4531;
1756         unsigned int idx;
1757         int err;
1758
1759         /* try reset AK4531 */
1760         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1761         inw(ES_REG(ensoniq, 1370_CODEC));
1762         udelay(100);
1763         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1764         inw(ES_REG(ensoniq, 1370_CODEC));
1765         udelay(100);
1766
1767         memset(&ak4531, 0, sizeof(ak4531));
1768         ak4531.write = snd_es1370_codec_write;
1769         ak4531.private_data = ensoniq;
1770         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1771         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1772                 return err;
1773         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1774                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1775                 if (err < 0)
1776                         return err;
1777         }
1778         return 0;
1779 }
1780
1781 #endif /* CHIP1370 */
1782
1783 #ifdef SUPPORT_JOYSTICK
1784
1785 #ifdef CHIP1371
1786 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1787 {
1788         switch (joystick_port[dev]) {
1789         case 0: /* disabled */
1790         case 1: /* auto-detect */
1791         case 0x200:
1792         case 0x208:
1793         case 0x210:
1794         case 0x218:
1795                 return joystick_port[dev];
1796
1797         default:
1798                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1799                 return 0;
1800         }
1801 }
1802 #else
1803 static inline int snd_ensoniq_get_joystick_port(int dev)
1804 {
1805         return joystick[dev] ? 0x200 : 0;
1806 }
1807 #endif
1808
1809 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1810 {
1811         struct gameport *gp;
1812         int io_port;
1813
1814         io_port = snd_ensoniq_get_joystick_port(dev);
1815
1816         switch (io_port) {
1817         case 0:
1818                 return -ENOSYS;
1819
1820         case 1: /* auto_detect */
1821                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1822                         if (request_region(io_port, 8, "ens137x: gameport"))
1823                                 break;
1824                 if (io_port > 0x218) {
1825                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1826                         return -EBUSY;
1827                 }
1828                 break;
1829
1830         default:
1831                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1832                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1833                                io_port);
1834                         return -EBUSY;
1835                 }
1836                 break;
1837         }
1838
1839         ensoniq->gameport = gp = gameport_allocate_port();
1840         if (!gp) {
1841                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1842                 release_region(io_port, 8);
1843                 return -ENOMEM;
1844         }
1845
1846         gameport_set_name(gp, "ES137x");
1847         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1848         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1849         gp->io = io_port;
1850
1851         ensoniq->ctrl |= ES_JYSTK_EN;
1852 #ifdef CHIP1371
1853         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1854         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1855 #endif
1856         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1857
1858         gameport_register_port(ensoniq->gameport);
1859
1860         return 0;
1861 }
1862
1863 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1864 {
1865         if (ensoniq->gameport) {
1866                 int port = ensoniq->gameport->io;
1867
1868                 gameport_unregister_port(ensoniq->gameport);
1869                 ensoniq->gameport = NULL;
1870                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1871                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1872                 release_region(port, 8);
1873         }
1874 }
1875 #else
1876 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1877 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1878 #endif /* SUPPORT_JOYSTICK */
1879
1880 /*
1881
1882  */
1883
1884 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1885                                   struct snd_info_buffer *buffer)
1886 {
1887         struct ensoniq *ensoniq = entry->private_data;
1888
1889 #ifdef CHIP1370
1890         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1891 #else
1892         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1893 #endif
1894         snd_iprintf(buffer, "Joystick enable  : %s\n",
1895                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1896 #ifdef CHIP1370
1897         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1898                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1899         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1900                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1901 #else
1902         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1903                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1904 #endif
1905 }
1906
1907 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1908 {
1909         struct snd_info_entry *entry;
1910
1911         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1912                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1913 }
1914
1915 /*
1916
1917  */
1918
1919 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1920 {
1921         snd_ensoniq_free_gameport(ensoniq);
1922         if (ensoniq->irq < 0)
1923                 goto __hw_end;
1924 #ifdef CHIP1370
1925         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1926         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1927 #else
1928         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1929         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1930 #endif
1931         synchronize_irq(ensoniq->irq);
1932         pci_set_power_state(ensoniq->pci, 3);
1933       __hw_end:
1934 #ifdef CHIP1370
1935         if (ensoniq->dma_bug.area)
1936                 snd_dma_free_pages(&ensoniq->dma_bug);
1937 #endif
1938         if (ensoniq->irq >= 0)
1939                 free_irq(ensoniq->irq, ensoniq);
1940         pci_release_regions(ensoniq->pci);
1941         pci_disable_device(ensoniq->pci);
1942         kfree(ensoniq);
1943         return 0;
1944 }
1945
1946 static int snd_ensoniq_dev_free(struct snd_device *device)
1947 {
1948         struct ensoniq *ensoniq = device->device_data;
1949         return snd_ensoniq_free(ensoniq);
1950 }
1951
1952 #ifdef CHIP1371
1953 static struct {
1954         unsigned short svid;            /* subsystem vendor ID */
1955         unsigned short sdid;            /* subsystem device ID */
1956 } es1371_amplifier_hack[] = {
1957         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1958         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1959         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1960         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1961         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1962 };
1963 static struct {
1964         unsigned short vid;             /* vendor ID */
1965         unsigned short did;             /* device ID */
1966         unsigned char rev;              /* revision */
1967 } es1371_ac97_reset_hack[] = {
1968         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1969         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1970         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1971         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1972         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1973         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1974 };
1975 #endif
1976
1977 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1978 {
1979 #ifdef CHIP1371
1980         int idx;
1981         struct pci_dev *pci = ensoniq->pci;
1982 #endif
1983         /* this code was part of snd_ensoniq_create before intruduction
1984           * of suspend/resume
1985           */
1986 #ifdef CHIP1370
1987         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1988         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1989         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1990         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1991         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1992 #else
1993         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1994         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1995         outl(0, ES_REG(ensoniq, 1371_LEGACY));
1996         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1997                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
1998                     pci->device == es1371_ac97_reset_hack[idx].did &&
1999                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2000                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2001                         /* need to delay around 20ms(bleech) to give
2002                         some CODECs enough time to wakeup */
2003                         msleep(20);
2004                         break;
2005                 }
2006         /* AC'97 warm reset to start the bitclk */
2007         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2008         inl(ES_REG(ensoniq, CONTROL));
2009         udelay(20);
2010         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2011         /* Init the sample rate converter */
2012         snd_es1371_wait_src_ready(ensoniq);
2013         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2014         for (idx = 0; idx < 0x80; idx++)
2015                 snd_es1371_src_write(ensoniq, idx, 0);
2016         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2017         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2018         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2019         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2020         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2021         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2022         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2023         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2024         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2025         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2026         snd_es1371_adc_rate(ensoniq, 22050);
2027         snd_es1371_dac1_rate(ensoniq, 22050);
2028         snd_es1371_dac2_rate(ensoniq, 22050);
2029         /* WARNING:
2030          * enabling the sample rate converter without properly programming
2031          * its parameters causes the chip to lock up (the SRC busy bit will
2032          * be stuck high, and I've found no way to rectify this other than
2033          * power cycle) - Thomas Sailer
2034          */
2035         snd_es1371_wait_src_ready(ensoniq);
2036         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2037         /* try reset codec directly */
2038         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2039 #endif
2040         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2041         outb(0x00, ES_REG(ensoniq, UART_RES));
2042         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2043         synchronize_irq(ensoniq->irq);
2044 }
2045
2046 #ifdef CONFIG_PM
2047 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2048 {
2049         struct snd_card *card = pci_get_drvdata(pci);
2050         struct ensoniq *ensoniq = card->private_data;
2051
2052         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2053
2054         snd_pcm_suspend_all(ensoniq->pcm1);
2055         snd_pcm_suspend_all(ensoniq->pcm2);
2056
2057 #ifdef CHIP1371
2058         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2059 #else
2060         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2061 #endif
2062         pci_set_power_state(pci, PCI_D3hot);
2063         pci_disable_device(pci);
2064         pci_save_state(pci);
2065         return 0;
2066 }
2067
2068 static int snd_ensoniq_resume(struct pci_dev *pci)
2069 {
2070         struct snd_card *card = pci_get_drvdata(pci);
2071         struct ensoniq *ensoniq = card->private_data;
2072
2073         pci_restore_state(pci);
2074         pci_enable_device(pci);
2075         pci_set_power_state(pci, PCI_D0);
2076         pci_set_master(pci);
2077
2078         snd_ensoniq_chip_init(ensoniq);
2079
2080 #ifdef CHIP1371
2081         snd_ac97_resume(ensoniq->u.es1371.ac97);
2082 #else
2083         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2084 #endif
2085         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2086         return 0;
2087 }
2088 #endif /* CONFIG_PM */
2089
2090
2091 static int __devinit snd_ensoniq_create(struct snd_card *card,
2092                                      struct pci_dev *pci,
2093                                      struct ensoniq ** rensoniq)
2094 {
2095         struct ensoniq *ensoniq;
2096         unsigned short cmdw;
2097         unsigned char cmdb;
2098 #ifdef CHIP1371
2099         int idx;
2100 #endif
2101         int err;
2102         static struct snd_device_ops ops = {
2103                 .dev_free =     snd_ensoniq_dev_free,
2104         };
2105
2106         *rensoniq = NULL;
2107         if ((err = pci_enable_device(pci)) < 0)
2108                 return err;
2109         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2110         if (ensoniq == NULL) {
2111                 pci_disable_device(pci);
2112                 return -ENOMEM;
2113         }
2114         spin_lock_init(&ensoniq->reg_lock);
2115         init_MUTEX(&ensoniq->src_mutex);
2116         ensoniq->card = card;
2117         ensoniq->pci = pci;
2118         ensoniq->irq = -1;
2119         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2120                 kfree(ensoniq);
2121                 pci_disable_device(pci);
2122                 return err;
2123         }
2124         ensoniq->port = pci_resource_start(pci, 0);
2125         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ,
2126                         "Ensoniq AudioPCI", ensoniq)) {
2127                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2128                 snd_ensoniq_free(ensoniq);
2129                 return -EBUSY;
2130         }
2131         ensoniq->irq = pci->irq;
2132 #ifdef CHIP1370
2133         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2134                                 16, &ensoniq->dma_bug) < 0) {
2135                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2136                 snd_ensoniq_free(ensoniq);
2137                 return -EBUSY;
2138         }
2139 #endif
2140         pci_set_master(pci);
2141         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2142         ensoniq->rev = cmdb;
2143         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2144         ensoniq->subsystem_vendor_id = cmdw;
2145         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2146         ensoniq->subsystem_device_id = cmdw;
2147 #ifdef CHIP1370
2148 #if 0
2149         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2150                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2151 #else   /* get microphone working */
2152         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2153 #endif
2154         ensoniq->sctrl = 0;
2155 #else
2156         ensoniq->ctrl = 0;
2157         ensoniq->sctrl = 0;
2158         ensoniq->cssr = 0;
2159         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2160                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2161                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2162                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2163                         break;
2164                 }
2165         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2166                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2167                     pci->device == es1371_ac97_reset_hack[idx].did &&
2168                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2169                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
2170                         break;
2171                 }
2172 #endif
2173
2174         snd_ensoniq_chip_init(ensoniq);
2175
2176         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2177                 snd_ensoniq_free(ensoniq);
2178                 return err;
2179         }
2180
2181         snd_ensoniq_proc_init(ensoniq);
2182
2183         snd_card_set_dev(card, &pci->dev);
2184
2185         *rensoniq = ensoniq;
2186         return 0;
2187 }
2188
2189 /*
2190  *  MIDI section
2191  */
2192
2193 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2194 {
2195         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2196         unsigned char status, mask, byte;
2197
2198         if (rmidi == NULL)
2199                 return;
2200         /* do Rx at first */
2201         spin_lock(&ensoniq->reg_lock);
2202         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2203         while (mask) {
2204                 status = inb(ES_REG(ensoniq, UART_STATUS));
2205                 if ((status & mask) == 0)
2206                         break;
2207                 byte = inb(ES_REG(ensoniq, UART_DATA));
2208                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2209         }
2210         spin_unlock(&ensoniq->reg_lock);
2211
2212         /* do Tx at second */
2213         spin_lock(&ensoniq->reg_lock);
2214         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2215         while (mask) {
2216                 status = inb(ES_REG(ensoniq, UART_STATUS));
2217                 if ((status & mask) == 0)
2218                         break;
2219                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2220                         ensoniq->uartc &= ~ES_TXINTENM;
2221                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2222                         mask &= ~ES_TXRDY;
2223                 } else {
2224                         outb(byte, ES_REG(ensoniq, UART_DATA));
2225                 }
2226         }
2227         spin_unlock(&ensoniq->reg_lock);
2228 }
2229
2230 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2231 {
2232         struct ensoniq *ensoniq = substream->rmidi->private_data;
2233
2234         spin_lock_irq(&ensoniq->reg_lock);
2235         ensoniq->uartm |= ES_MODE_INPUT;
2236         ensoniq->midi_input = substream;
2237         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2238                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2239                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2240                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2241         }
2242         spin_unlock_irq(&ensoniq->reg_lock);
2243         return 0;
2244 }
2245
2246 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2247 {
2248         struct ensoniq *ensoniq = substream->rmidi->private_data;
2249
2250         spin_lock_irq(&ensoniq->reg_lock);
2251         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2252                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2253                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2254         } else {
2255                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2256         }
2257         ensoniq->midi_input = NULL;
2258         ensoniq->uartm &= ~ES_MODE_INPUT;
2259         spin_unlock_irq(&ensoniq->reg_lock);
2260         return 0;
2261 }
2262
2263 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2264 {
2265         struct ensoniq *ensoniq = substream->rmidi->private_data;
2266
2267         spin_lock_irq(&ensoniq->reg_lock);
2268         ensoniq->uartm |= ES_MODE_OUTPUT;
2269         ensoniq->midi_output = substream;
2270         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2271                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2272                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2273                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2274         }
2275         spin_unlock_irq(&ensoniq->reg_lock);
2276         return 0;
2277 }
2278
2279 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2280 {
2281         struct ensoniq *ensoniq = substream->rmidi->private_data;
2282
2283         spin_lock_irq(&ensoniq->reg_lock);
2284         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2285                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2286                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2287         } else {
2288                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2289         }
2290         ensoniq->midi_output = NULL;
2291         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2292         spin_unlock_irq(&ensoniq->reg_lock);
2293         return 0;
2294 }
2295
2296 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2297 {
2298         unsigned long flags;
2299         struct ensoniq *ensoniq = substream->rmidi->private_data;
2300         int idx;
2301
2302         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2303         if (up) {
2304                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2305                         /* empty input FIFO */
2306                         for (idx = 0; idx < 32; idx++)
2307                                 inb(ES_REG(ensoniq, UART_DATA));
2308                         ensoniq->uartc |= ES_RXINTEN;
2309                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2310                 }
2311         } else {
2312                 if (ensoniq->uartc & ES_RXINTEN) {
2313                         ensoniq->uartc &= ~ES_RXINTEN;
2314                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2315                 }
2316         }
2317         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2318 }
2319
2320 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2321 {
2322         unsigned long flags;
2323         struct ensoniq *ensoniq = substream->rmidi->private_data;
2324         unsigned char byte;
2325
2326         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2327         if (up) {
2328                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2329                         ensoniq->uartc |= ES_TXINTENO(1);
2330                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2331                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2332                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2333                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2334                                         ensoniq->uartc &= ~ES_TXINTENM;
2335                                 } else {
2336                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2337                                 }
2338                         }
2339                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2340                 }
2341         } else {
2342                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2343                         ensoniq->uartc &= ~ES_TXINTENM;
2344                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2345                 }
2346         }
2347         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2348 }
2349
2350 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2351 {
2352         .open =         snd_ensoniq_midi_output_open,
2353         .close =        snd_ensoniq_midi_output_close,
2354         .trigger =      snd_ensoniq_midi_output_trigger,
2355 };
2356
2357 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2358 {
2359         .open =         snd_ensoniq_midi_input_open,
2360         .close =        snd_ensoniq_midi_input_close,
2361         .trigger =      snd_ensoniq_midi_input_trigger,
2362 };
2363
2364 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2365                                       struct snd_rawmidi **rrawmidi)
2366 {
2367         struct snd_rawmidi *rmidi;
2368         int err;
2369
2370         if (rrawmidi)
2371                 *rrawmidi = NULL;
2372         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2373                 return err;
2374 #ifdef CHIP1370
2375         strcpy(rmidi->name, "ES1370");
2376 #else
2377         strcpy(rmidi->name, "ES1371");
2378 #endif
2379         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2380         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2381         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2382                 SNDRV_RAWMIDI_INFO_DUPLEX;
2383         rmidi->private_data = ensoniq;
2384         ensoniq->rmidi = rmidi;
2385         if (rrawmidi)
2386                 *rrawmidi = rmidi;
2387         return 0;
2388 }
2389
2390 /*
2391  *  Interrupt handler
2392  */
2393
2394 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2395 {
2396         struct ensoniq *ensoniq = dev_id;
2397         unsigned int status, sctrl;
2398
2399         if (ensoniq == NULL)
2400                 return IRQ_NONE;
2401
2402         status = inl(ES_REG(ensoniq, STATUS));
2403         if (!(status & ES_INTR))
2404                 return IRQ_NONE;
2405
2406         spin_lock(&ensoniq->reg_lock);
2407         sctrl = ensoniq->sctrl;
2408         if (status & ES_DAC1)
2409                 sctrl &= ~ES_P1_INT_EN;
2410         if (status & ES_DAC2)
2411                 sctrl &= ~ES_P2_INT_EN;
2412         if (status & ES_ADC)
2413                 sctrl &= ~ES_R1_INT_EN;
2414         outl(sctrl, ES_REG(ensoniq, SERIAL));
2415         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2416         spin_unlock(&ensoniq->reg_lock);
2417
2418         if (status & ES_UART)
2419                 snd_ensoniq_midi_interrupt(ensoniq);
2420         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2421                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2422         if ((status & ES_ADC) && ensoniq->capture_substream)
2423                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2424         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2425                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2426         return IRQ_HANDLED;
2427 }
2428
2429 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2430                                         const struct pci_device_id *pci_id)
2431 {
2432         static int dev;
2433         struct snd_card *card;
2434         struct ensoniq *ensoniq;
2435         int err, pcm_devs[2];
2436
2437         if (dev >= SNDRV_CARDS)
2438                 return -ENODEV;
2439         if (!enable[dev]) {
2440                 dev++;
2441                 return -ENOENT;
2442         }
2443
2444         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2445         if (card == NULL)
2446                 return -ENOMEM;
2447
2448         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2449                 snd_card_free(card);
2450                 return err;
2451         }
2452         card->private_data = ensoniq;
2453
2454         pcm_devs[0] = 0; pcm_devs[1] = 1;
2455 #ifdef CHIP1370
2456         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2457                 snd_card_free(card);
2458                 return err;
2459         }
2460 #endif
2461 #ifdef CHIP1371
2462         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2463                 snd_card_free(card);
2464                 return err;
2465         }
2466 #endif
2467         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2468                 snd_card_free(card);
2469                 return err;
2470         }
2471         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2472                 snd_card_free(card);
2473                 return err;
2474         }
2475         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2476                 snd_card_free(card);
2477                 return err;
2478         }
2479
2480         snd_ensoniq_create_gameport(ensoniq, dev);
2481
2482         strcpy(card->driver, DRIVER_NAME);
2483
2484         strcpy(card->shortname, "Ensoniq AudioPCI");
2485         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2486                 card->shortname,
2487                 card->driver,
2488                 ensoniq->port,
2489                 ensoniq->irq);
2490
2491         if ((err = snd_card_register(card)) < 0) {
2492                 snd_card_free(card);
2493                 return err;
2494         }
2495
2496         pci_set_drvdata(pci, card);
2497         dev++;
2498         return 0;
2499 }
2500
2501 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2502 {
2503         snd_card_free(pci_get_drvdata(pci));
2504         pci_set_drvdata(pci, NULL);
2505 }
2506
2507 static struct pci_driver driver = {
2508         .name = DRIVER_NAME,
2509         .id_table = snd_audiopci_ids,
2510         .probe = snd_audiopci_probe,
2511         .remove = __devexit_p(snd_audiopci_remove),
2512 #ifdef CONFIG_PM
2513         .suspend = snd_ensoniq_suspend,
2514         .resume = snd_ensoniq_resume,
2515 #endif
2516 };
2517
2518 static int __init alsa_card_ens137x_init(void)
2519 {
2520         return pci_register_driver(&driver);
2521 }
2522
2523 static void __exit alsa_card_ens137x_exit(void)
2524 {
2525         pci_unregister_driver(&driver);
2526 }
2527
2528 module_init(alsa_card_ens137x_init)
2529 module_exit(alsa_card_ens137x_exit)