2 * SAS structures and definitions header file
4 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
7 * This file is licensed under GPLv2.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 #include <linux/types.h>
30 #include <asm/byteorder.h>
32 #define SAS_ADDR_SIZE 8
33 #define HASHED_SAS_ADDR_SIZE 3
34 #define SAS_ADDR(_sa) ((unsigned long long) be64_to_cpu(*(__be64 *)(_sa)))
36 #define SMP_REQUEST 0x40
37 #define SMP_RESPONSE 0x41
40 #define SSP_XFER_RDY 0x05
41 #define SSP_COMMAND 0x06
42 #define SSP_RESPONSE 0x07
45 #define SMP_REPORT_GENERAL 0x00
46 #define SMP_REPORT_MANUF_INFO 0x01
47 #define SMP_READ_GPIO_REG 0x02
48 #define SMP_DISCOVER 0x10
49 #define SMP_REPORT_PHY_ERR_LOG 0x11
50 #define SMP_REPORT_PHY_SATA 0x12
51 #define SMP_REPORT_ROUTE_INFO 0x13
52 #define SMP_WRITE_GPIO_REG 0x82
53 #define SMP_CONF_ROUTE_INFO 0x90
54 #define SMP_PHY_CONTROL 0x91
55 #define SMP_PHY_TEST_FUNCTION 0x92
57 #define SMP_RESP_FUNC_ACC 0x00
58 #define SMP_RESP_FUNC_UNK 0x01
59 #define SMP_RESP_FUNC_FAILED 0x02
60 #define SMP_RESP_INV_FRM_LEN 0x03
61 #define SMP_RESP_NO_PHY 0x10
62 #define SMP_RESP_NO_INDEX 0x11
63 #define SMP_RESP_PHY_NO_SATA 0x12
64 #define SMP_RESP_PHY_UNK_OP 0x13
65 #define SMP_RESP_PHY_UNK_TESTF 0x14
66 #define SMP_RESP_PHY_TEST_INPROG 0x15
67 #define SMP_RESP_PHY_VACANT 0x16
70 #define TMF_ABORT_TASK 0x01
71 #define TMF_ABORT_TASK_SET 0x02
72 #define TMF_CLEAR_TASK_SET 0x04
73 #define TMF_LU_RESET 0x08
74 #define TMF_CLEAR_ACA 0x40
75 #define TMF_QUERY_TASK 0x80
77 /* SAS TMF responses */
78 #define TMF_RESP_FUNC_COMPLETE 0x00
79 #define TMF_RESP_INVALID_FRAME 0x02
80 #define TMF_RESP_FUNC_ESUPP 0x04
81 #define TMF_RESP_FUNC_FAILED 0x05
82 #define TMF_RESP_FUNC_SUCC 0x08
83 #define TMF_RESP_NO_LUN 0x09
84 #define TMF_RESP_OVERLAPPED_TAG 0x0A
92 /* See sas_discover.c if you plan on changing these.
95 NO_DEVICE = 0, /* protocol */
96 SAS_END_DEV = 1, /* protocol */
97 EDGE_DEV = 2, /* protocol */
98 FANOUT_DEV = 3, /* protocol */
105 enum sas_phy_linkrate {
106 PHY_LINKRATE_NONE = 0,
107 PHY_LINKRATE_UNKNOWN = 0,
112 PHY_LINKRATE_1_5 = 0x08,
113 PHY_LINKRATE_G1 = PHY_LINKRATE_1_5,
114 PHY_LINKRATE_3 = 0x09,
115 PHY_LINKRATE_G2 = PHY_LINKRATE_3,
116 PHY_LINKRATE_6 = 0x0A,
119 /* Partly from IDENTIFY address frame. */
122 SAS_PROTO_SMP = 2, /* protocol */
123 SAS_PROTO_STP = 4, /* protocol */
124 SAS_PROTO_SSP = 8, /* protocol */
128 /* From the spec; local phys only */
131 PHY_FUNC_LINK_RESET, /* Enables the phy */
134 PHY_FUNC_CLEAR_ERROR_LOG = 5,
135 PHY_FUNC_CLEAR_AFFIL,
136 PHY_FUNC_TX_SATA_PS_SIGNAL,
137 PHY_FUNC_RELEASE_SPINUP_HOLD = 0x10, /* LOCAL PORT ONLY! */
140 /* SAS LLDD would need to report only _very_few_ of those, like BROADCAST.
141 * Most of those are here for completeness.
144 SAS_PRIM_AIP_NORMAL = 1,
151 SAS_PRIM_AIP_RWP = 8,
154 SAS_PRIM_BC_RCH0 = 10,
155 SAS_PRIM_BC_RCH1 = 11,
162 SAS_PRIM_NOTIFY_ENSP= 17,
163 SAS_PRIM_NOTIFY_R0 = 18,
164 SAS_PRIM_NOTIFY_R1 = 19,
165 SAS_PRIM_NOTIFY_R2 = 20,
167 SAS_PRIM_CLOSE_CLAF = 21,
168 SAS_PRIM_CLOSE_NORM = 22,
169 SAS_PRIM_CLOSE_R0 = 23,
170 SAS_PRIM_CLOSE_R1 = 24,
172 SAS_PRIM_OPEN_RTRY = 25,
173 SAS_PRIM_OPEN_RJCT = 26,
174 SAS_PRIM_OPEN_ACPT = 27,
180 SATA_PRIM_PMNAK = 34,
181 SATA_PRIM_PMACK = 35,
182 SATA_PRIM_PMREQ_S = 36,
183 SATA_PRIM_PMREQ_P = 37,
184 SATA_SATA_R_ERR = 38,
187 enum sas_open_rej_reason {
189 SAS_OREJ_UNKNOWN = 0,
190 SAS_OREJ_BAD_DEST = 1,
191 SAS_OREJ_CONN_RATE = 2,
193 SAS_OREJ_RESV_AB0 = 4,
194 SAS_OREJ_RESV_AB1 = 5,
195 SAS_OREJ_RESV_AB2 = 6,
196 SAS_OREJ_RESV_AB3 = 7,
197 SAS_OREJ_WRONG_DEST= 8,
198 SAS_OREJ_STP_NORES = 9,
201 SAS_OREJ_NO_DEST = 10,
202 SAS_OREJ_PATH_BLOCKED = 11,
203 SAS_OREJ_RSVD_CONT0 = 12,
204 SAS_OREJ_RSVD_CONT1 = 13,
205 SAS_OREJ_RSVD_INIT0 = 14,
206 SAS_OREJ_RSVD_INIT1 = 15,
207 SAS_OREJ_RSVD_STOP0 = 16,
208 SAS_OREJ_RSVD_STOP1 = 17,
209 SAS_OREJ_RSVD_RETRY = 18,
212 struct dev_to_host_fis {
213 u8 fis_type; /* 0x34 */
219 union { u8 lbam; u8 byte_count_low; };
220 union { u8 lbah; u8 byte_count_high; };
228 union { u8 sector_count; u8 interrupt_reason; };
234 } __attribute__ ((packed));
236 struct host_to_dev_fis {
237 u8 fis_type; /* 0x27 */
243 union { u8 lbam; u8 byte_count_low; };
244 union { u8 lbah; u8 byte_count_high; };
252 union { u8 sector_count; u8 interrupt_reason; };
258 } __attribute__ ((packed));
260 /* Prefer to have code clarity over header file clarity.
262 #ifdef __LITTLE_ENDIAN_BITFIELD
263 struct sas_identify_frame {
300 u8 sas_addr[SAS_ADDR_SIZE];
308 } __attribute__ ((packed));
310 struct ssp_frame_hdr {
312 u8 hashed_dest_addr[HASHED_SAS_ADDR_SIZE];
314 u8 hashed_src_addr[HASHED_SAS_ADDR_SIZE];
317 u8 changing_data_ptr:1;
319 u8 retry_data_frames:1;
329 } __attribute__ ((packed));
331 struct ssp_response_iu {
341 __be32 sense_data_len;
342 __be32 response_data_len;
346 } __attribute__ ((packed));
348 /* ---------- SMP ---------- */
350 struct report_general_resp {
352 __be16 route_indexes;
356 u8 conf_route_table:1;
362 u8 enclosure_logical_id[8];
365 } __attribute__ ((packed));
367 struct discover_resp {
374 u8 attached_dev_type:3;
380 u8 attached_sata_host:1;
384 u8 attached_sata_dev:1;
387 u8 attached_sata_ps:1;
390 u8 attached_sas_addr[8];
414 } __attribute__ ((packed));
416 struct report_phy_sata_resp {
430 struct dev_to_host_fis fis;
434 u8 affil_stp_ini_addr[8];
437 } __attribute__ ((packed));
445 struct report_general_resp rg;
446 struct discover_resp disc;
447 struct report_phy_sata_resp rps;
449 } __attribute__ ((packed));
451 #elif defined(__BIG_ENDIAN_BITFIELD)
452 struct sas_identify_frame {
489 u8 sas_addr[SAS_ADDR_SIZE];
497 } __attribute__ ((packed));
499 struct ssp_frame_hdr {
501 u8 hashed_dest_addr[HASHED_SAS_ADDR_SIZE];
503 u8 hashed_src_addr[HASHED_SAS_ADDR_SIZE];
507 u8 retry_data_frames:1;
509 u8 changing_data_ptr:1;
518 } __attribute__ ((packed));
520 struct ssp_response_iu {
530 __be32 sense_data_len;
531 __be32 response_data_len;
535 } __attribute__ ((packed));
537 /* ---------- SMP ---------- */
539 struct report_general_resp {
541 __be16 route_indexes;
547 u8 conf_route_table:1;
551 u8 enclosure_logical_id[8];
554 } __attribute__ ((packed));
556 struct discover_resp {
563 u8 attached_dev_type:3;
571 u8 attached_sata_host:1;
573 u8 attached_sata_ps:1;
576 u8 attached_sata_dev:1;
579 u8 attached_sas_addr[8];
603 } __attribute__ ((packed));
605 struct report_phy_sata_resp {
619 struct dev_to_host_fis fis;
623 u8 affil_stp_ini_addr[8];
626 } __attribute__ ((packed));
634 struct report_general_resp rg;
635 struct discover_resp disc;
636 struct report_phy_sata_resp rps;
638 } __attribute__ ((packed));
641 #error "Bitfield order not defined!"