2 * Copyright (C) 2005 David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * INTERFACES between SPI master-side drivers and SPI infrastructure.
24 * (There's no SPI slave support for Linux yet...)
26 extern struct bus_type spi_bus_type;
29 * struct spi_device - Master side proxy for an SPI slave device
30 * @dev: Driver model representation of the device.
31 * @master: SPI controller used with the device.
32 * @max_speed_hz: Maximum clock rate to be used with this chip
33 * (on this board); may be changed by the device's driver.
34 * The spi_transfer.speed_hz can override this for each transfer.
35 * @chip-select: Chipselect, distinguishing chips handled by "master".
36 * @mode: The spi mode defines how data is clocked out and in.
37 * This may be changed by the device's driver.
38 * The "active low" default for chipselect mode can be overridden,
39 * as can the "MSB first" default for each word in a transfer.
40 * @bits_per_word: Data transfers involve one or more words; word sizes
41 * like eight or 12 bits are common. In-memory wordsizes are
42 * powers of two bytes (e.g. 20 bit samples use 32 bits).
43 * This may be changed by the device's driver, or left at the
44 * default (0) indicating protocol words are eight bit bytes.
45 * The spi_transfer.bits_per_word can override this for each transfer.
46 * @irq: Negative, or the number passed to request_irq() to receive
47 * interrupts from this device.
48 * @controller_state: Controller's runtime state
49 * @controller_data: Board-specific definitions for controller, such as
50 * FIFO initialization parameters; from board_info.controller_data
52 * An spi_device is used to interchange data between an SPI slave
53 * (usually a discrete chip) and CPU memory.
55 * In "dev", the platform_data is used to hold information about this
56 * device that's meaningful to the device's protocol driver, but not
57 * to its controller. One example might be an identifier for a chip
58 * variant with slightly different functionality.
62 struct spi_master *master;
66 #define SPI_CPHA 0x01 /* clock phase */
67 #define SPI_CPOL 0x02 /* clock polarity */
68 #define SPI_MODE_0 (0|0) /* (original MicroWire) */
69 #define SPI_MODE_1 (0|SPI_CPHA)
70 #define SPI_MODE_2 (SPI_CPOL|0)
71 #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
72 #define SPI_CS_HIGH 0x04 /* chipselect active high? */
73 #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
76 void *controller_state;
77 void *controller_data;
80 // likely need more hooks for more protocol options affecting how
81 // the controller talks to each chip, like:
82 // - memory packing (12 bit samples into low bits, others zeroed)
84 // - drop chipselect after each word
85 // - chipselect delays
89 static inline struct spi_device *to_spi_device(struct device *dev)
91 return dev ? container_of(dev, struct spi_device, dev) : NULL;
94 /* most drivers won't need to care about device refcounting */
95 static inline struct spi_device *spi_dev_get(struct spi_device *spi)
97 return (spi && get_device(&spi->dev)) ? spi : NULL;
100 static inline void spi_dev_put(struct spi_device *spi)
103 put_device(&spi->dev);
106 /* ctldata is for the bus_master driver's runtime state */
107 static inline void *spi_get_ctldata(struct spi_device *spi)
109 return spi->controller_state;
112 static inline void spi_set_ctldata(struct spi_device *spi, void *state)
114 spi->controller_state = state;
117 /* device driver data */
119 static inline void spi_set_drvdata(struct spi_device *spi, void *data)
121 dev_set_drvdata(&spi->dev, data);
124 static inline void *spi_get_drvdata(struct spi_device *spi)
126 return dev_get_drvdata(&spi->dev);
134 int (*probe)(struct spi_device *spi);
135 int (*remove)(struct spi_device *spi);
136 void (*shutdown)(struct spi_device *spi);
137 int (*suspend)(struct spi_device *spi, pm_message_t mesg);
138 int (*resume)(struct spi_device *spi);
139 struct device_driver driver;
142 static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
144 return drv ? container_of(drv, struct spi_driver, driver) : NULL;
147 extern int spi_register_driver(struct spi_driver *sdrv);
149 static inline void spi_unregister_driver(struct spi_driver *sdrv)
152 driver_unregister(&sdrv->driver);
157 * struct spi_master - interface to SPI master controller
158 * @cdev: class interface to this driver
159 * @bus_num: board-specific (and often SOC-specific) identifier for a
160 * given SPI controller.
161 * @num_chipselect: chipselects are used to distinguish individual
162 * SPI slaves, and are numbered from zero to num_chipselects.
163 * each slave has a chipselect signal, but it's common that not
164 * every chipselect is connected to a slave.
165 * @setup: updates the device mode and clocking records used by a
166 * device's SPI controller; protocol code may call this. This
167 * must fail if an unrecognized or unsupported mode is requested.
168 * @transfer: adds a message to the controller's transfer queue.
169 * @cleanup: frees controller-specific state
171 * Each SPI master controller can communicate with one or more spi_device
172 * children. These make a small bus, sharing MOSI, MISO and SCK signals
173 * but not chip select signals. Each device may be configured to use a
174 * different clock rate, since those shared signals are ignored unless
175 * the chip is selected.
177 * The driver for an SPI controller manages access to those devices through
178 * a queue of spi_message transactions, copyin data between CPU memory and
179 * an SPI slave device). For each such message it queues, it calls the
180 * message's completion function when the transaction completes.
183 struct class_device cdev;
185 /* other than negative (== assign one dynamically), bus_num is fully
186 * board-specific. usually that simplifies to being SOC-specific.
187 * example: one SOC has three SPI controllers, numbered 0..2,
188 * and one board's schematics might show it using SPI-2. software
189 * would normally use bus_num=2 for that controller.
193 /* chipselects will be integral to many controllers; some others
194 * might use board-specific GPIOs.
198 /* setup mode and clock, etc (spi driver may call many times) */
199 int (*setup)(struct spi_device *spi);
201 /* bidirectional bulk transfers
203 * + The transfer() method may not sleep; its main role is
204 * just to add the message to the queue.
205 * + For now there's no remove-from-queue operation, or
206 * any other request management
207 * + To a given spi_device, message queueing is pure fifo
209 * + The master's main job is to process its message queue,
210 * selecting a chip then transferring data
211 * + If there are multiple spi_device children, the i/o queue
212 * arbitration algorithm is unspecified (round robin, fifo,
213 * priority, reservations, preemption, etc)
215 * + Chipselect stays active during the entire message
216 * (unless modified by spi_transfer.cs_change != 0).
217 * + The message transfers use clock and SPI mode parameters
218 * previously established by setup() for this device
220 int (*transfer)(struct spi_device *spi,
221 struct spi_message *mesg);
223 /* called on release() to free memory provided by spi_master */
224 void (*cleanup)(struct spi_device *spi);
227 static inline void *spi_master_get_devdata(struct spi_master *master)
229 return class_get_devdata(&master->cdev);
232 static inline void spi_master_set_devdata(struct spi_master *master, void *data)
234 class_set_devdata(&master->cdev, data);
237 static inline struct spi_master *spi_master_get(struct spi_master *master)
239 if (!master || !class_device_get(&master->cdev))
244 static inline void spi_master_put(struct spi_master *master)
247 class_device_put(&master->cdev);
251 /* the spi driver core manages memory for the spi_master classdev */
252 extern struct spi_master *
253 spi_alloc_master(struct device *host, unsigned size);
255 extern int spi_register_master(struct spi_master *master);
256 extern void spi_unregister_master(struct spi_master *master);
258 extern struct spi_master *spi_busnum_to_master(u16 busnum);
260 /*---------------------------------------------------------------------------*/
263 * I/O INTERFACE between SPI controller and protocol drivers
265 * Protocol drivers use a queue of spi_messages, each transferring data
266 * between the controller and memory buffers.
268 * The spi_messages themselves consist of a series of read+write transfer
269 * segments. Those segments always read the same number of bits as they
270 * write; but one or the other is easily ignored by passing a null buffer
271 * pointer. (This is unlike most types of I/O API, because SPI hardware
274 * NOTE: Allocation of spi_transfer and spi_message memory is entirely
275 * up to the protocol driver, which guarantees the integrity of both (as
276 * well as the data buffers) for as long as the message is queued.
280 * struct spi_transfer - a read/write buffer pair
281 * @tx_buf: data to be written (dma-safe memory), or NULL
282 * @rx_buf: data to be read (dma-safe memory), or NULL
283 * @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
284 * @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
285 * @len: size of rx and tx buffers (in bytes)
286 * @speed_hz: Select a speed other then the device default for this
287 * transfer. If 0 the default (from spi_device) is used.
288 * @bits_per_word: select a bits_per_word other then the device default
289 * for this transfer. If 0 the default (from spi_device) is used.
290 * @cs_change: affects chipselect after this transfer completes
291 * @delay_usecs: microseconds to delay after this transfer before
292 * (optionally) changing the chipselect status, then starting
293 * the next transfer or completing this spi_message.
294 * @transfer_list: transfers are sequenced through spi_message.transfers
296 * SPI transfers always write the same number of bytes as they read.
297 * Protocol drivers should always provide rx_buf and/or tx_buf.
298 * In some cases, they may also want to provide DMA addresses for
299 * the data being transferred; that may reduce overhead, when the
300 * underlying driver uses dma.
302 * If the transmit buffer is null, zeroes will be shifted out
303 * while filling rx_buf. If the receive buffer is null, the data
304 * shifted in will be discarded. Only "len" bytes shift out (or in).
305 * It's an error to try to shift out a partial word. (For example, by
306 * shifting out three bytes with word size of sixteen or twenty bits;
307 * the former uses two bytes per word, the latter uses four bytes.)
309 * In-memory data values are always in native CPU byte order, translated
310 * from the wire byte order (big-endian except with SPI_LSB_FIRST). So
311 * for example when bits_per_word is sixteen, buffers are 2N bytes long
312 * and hold N sixteen bit words in CPU byte order.
314 * When the word size of the SPI transfer is not a power-of-two multiple
315 * of eight bits, those in-memory words include extra bits. In-memory
316 * words are always seen by protocol drivers as right-justified, so the
317 * undefined (rx) or unused (tx) bits are always the most significant bits.
319 * All SPI transfers start with the relevant chipselect active. Normally
320 * it stays selected until after the last transfer in a message. Drivers
321 * can affect the chipselect signal using cs_change:
323 * (i) If the transfer isn't the last one in the message, this flag is
324 * used to make the chipselect briefly go inactive in the middle of the
325 * message. Toggling chipselect in this way may be needed to terminate
326 * a chip command, letting a single spi_message perform all of group of
327 * chip transactions together.
329 * (ii) When the transfer is the last one in the message, the chip may
330 * stay selected until the next transfer. This is purely a performance
331 * hint; the controller driver may need to select a different device
332 * for the next message.
334 * The code that submits an spi_message (and its spi_transfers)
335 * to the lower layers is responsible for managing its memory.
336 * Zero-initialize every field you don't set up explicitly, to
337 * insulate against future API updates. After you submit a message
338 * and its transfers, ignore them until its completion callback.
340 struct spi_transfer {
341 /* it's ok if tx_buf == rx_buf (right?)
342 * for MicroWire, one buffer must be null
343 * buffers must work with dma_*map_single() calls, unless
344 * spi_message.is_dma_mapped reports a pre-existing mapping
353 unsigned cs_change:1;
358 struct list_head transfer_list;
362 * struct spi_message - one multi-segment SPI transaction
363 * @transfers: list of transfer segments in this transaction
364 * @spi: SPI device to which the transaction is queued
365 * @is_dma_mapped: if true, the caller provided both dma and cpu virtual
366 * addresses for each transfer buffer
367 * @complete: called to report transaction completions
368 * @context: the argument to complete() when it's called
369 * @actual_length: the total number of bytes that were transferred in all
370 * successful segments
371 * @status: zero for success, else negative errno
372 * @queue: for use by whichever driver currently owns the message
373 * @state: for use by whichever driver currently owns the message
375 * An spi_message is used to execute an atomic sequence of data transfers,
376 * each represented by a struct spi_transfer. The sequence is "atomic"
377 * in the sense that no other spi_message may use that SPI bus until that
378 * sequence completes. On some systems, many such sequences can execute as
379 * as single programmed DMA transfer. On all systems, these messages are
380 * queued, and might complete after transactions to other devices. Messages
381 * sent to a given spi_device are alway executed in FIFO order.
383 * The code that submits an spi_message (and its spi_transfers)
384 * to the lower layers is responsible for managing its memory.
385 * Zero-initialize every field you don't set up explicitly, to
386 * insulate against future API updates. After you submit a message
387 * and its transfers, ignore them until its completion callback.
390 struct list_head transfers;
392 struct spi_device *spi;
394 unsigned is_dma_mapped:1;
396 /* REVISIT: we might want a flag affecting the behavior of the
397 * last transfer ... allowing things like "read 16 bit length L"
398 * immediately followed by "read L bytes". Basically imposing
399 * a specific message scheduling algorithm.
401 * Some controller drivers (message-at-a-time queue processing)
402 * could provide that as their default scheduling algorithm. But
403 * others (with multi-message pipelines) could need a flag to
404 * tell them about such special cases.
407 /* completion is reported through a callback */
408 void (*complete)(void *context);
410 unsigned actual_length;
413 /* for optional use by whatever driver currently owns the
414 * spi_message ... between calls to spi_async and then later
415 * complete(), that's the spi_master controller driver.
417 struct list_head queue;
421 static inline void spi_message_init(struct spi_message *m)
423 memset(m, 0, sizeof *m);
424 INIT_LIST_HEAD(&m->transfers);
428 spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
430 list_add_tail(&t->transfer_list, &m->transfers);
434 spi_transfer_del(struct spi_transfer *t)
436 list_del(&t->transfer_list);
439 /* It's fine to embed message and transaction structures in other data
440 * structures so long as you don't free them while they're in use.
443 static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags)
445 struct spi_message *m;
447 m = kzalloc(sizeof(struct spi_message)
448 + ntrans * sizeof(struct spi_transfer),
452 struct spi_transfer *t = (struct spi_transfer *)(m + 1);
454 INIT_LIST_HEAD(&m->transfers);
455 for (i = 0; i < ntrans; i++, t++)
456 spi_message_add_tail(t, m);
461 static inline void spi_message_free(struct spi_message *m)
467 * spi_setup -- setup SPI mode and clock rate
468 * @spi: the device whose settings are being modified
470 * SPI protocol drivers may need to update the transfer mode if the
471 * device doesn't work with the mode 0 default. They may likewise need
472 * to update clock rates or word sizes from initial values. This function
473 * changes those settings, and must be called from a context that can sleep.
474 * The changes take effect the next time the device is selected and data
475 * is transferred to or from it.
477 * Note that this call wil fail if the protocol driver specifies an option
478 * that the underlying controller or its driver does not support. For
479 * example, not all hardware supports wire transfers using nine bit words,
480 * LSB-first wire encoding, or active-high chipselects.
483 spi_setup(struct spi_device *spi)
485 return spi->master->setup(spi);
490 * spi_async -- asynchronous SPI transfer
491 * @spi: device with which data will be exchanged
492 * @message: describes the data transfers, including completion callback
494 * This call may be used in_irq and other contexts which can't sleep,
495 * as well as from task contexts which can sleep.
497 * The completion callback is invoked in a context which can't sleep.
498 * Before that invocation, the value of message->status is undefined.
499 * When the callback is issued, message->status holds either zero (to
500 * indicate complete success) or a negative error code. After that
501 * callback returns, the driver which issued the transfer request may
502 * deallocate the associated memory; it's no longer in use by any SPI
503 * core or controller driver code.
505 * Note that although all messages to a spi_device are handled in
506 * FIFO order, messages may go to different devices in other orders.
507 * Some device might be higher priority, or have various "hard" access
508 * time requirements, for example.
510 * On detection of any fault during the transfer, processing of
511 * the entire message is aborted, and the device is deselected.
512 * Until returning from the associated message completion callback,
513 * no other spi_message queued to that device will be processed.
514 * (This rule applies equally to all the synchronous transfer calls,
515 * which are wrappers around this core asynchronous primitive.)
518 spi_async(struct spi_device *spi, struct spi_message *message)
521 return spi->master->transfer(spi, message);
524 /*---------------------------------------------------------------------------*/
526 /* All these synchronous SPI transfer routines are utilities layered
527 * over the core async transfer primitive. Here, "synchronous" means
528 * they will sleep uninterruptibly until the async transfer completes.
531 extern int spi_sync(struct spi_device *spi, struct spi_message *message);
534 * spi_write - SPI synchronous write
535 * @spi: device to which data will be written
537 * @len: data buffer size
539 * This writes the buffer and returns zero or a negative error code.
540 * Callable only from contexts that can sleep.
543 spi_write(struct spi_device *spi, const u8 *buf, size_t len)
545 struct spi_transfer t = {
549 struct spi_message m;
551 spi_message_init(&m);
552 spi_message_add_tail(&t, &m);
553 return spi_sync(spi, &m);
557 * spi_read - SPI synchronous read
558 * @spi: device from which data will be read
560 * @len: data buffer size
562 * This writes the buffer and returns zero or a negative error code.
563 * Callable only from contexts that can sleep.
566 spi_read(struct spi_device *spi, u8 *buf, size_t len)
568 struct spi_transfer t = {
572 struct spi_message m;
574 spi_message_init(&m);
575 spi_message_add_tail(&t, &m);
576 return spi_sync(spi, &m);
579 /* this copies txbuf and rxbuf data; for small transfers only! */
580 extern int spi_write_then_read(struct spi_device *spi,
581 const u8 *txbuf, unsigned n_tx,
582 u8 *rxbuf, unsigned n_rx);
585 * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
586 * @spi: device with which data will be exchanged
587 * @cmd: command to be written before data is read back
589 * This returns the (unsigned) eight bit number returned by the
590 * device, or else a negative error code. Callable only from
591 * contexts that can sleep.
593 static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
598 status = spi_write_then_read(spi, &cmd, 1, &result, 1);
600 /* return negative errno or unsigned value */
601 return (status < 0) ? status : result;
605 * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
606 * @spi: device with which data will be exchanged
607 * @cmd: command to be written before data is read back
609 * This returns the (unsigned) sixteen bit number returned by the
610 * device, or else a negative error code. Callable only from
611 * contexts that can sleep.
613 * The number is returned in wire-order, which is at least sometimes
616 static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd)
621 status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2);
623 /* return negative errno or unsigned value */
624 return (status < 0) ? status : result;
627 /*---------------------------------------------------------------------------*/
630 * INTERFACE between board init code and SPI infrastructure.
632 * No SPI driver ever sees these SPI device table segments, but
633 * it's how the SPI core (or adapters that get hotplugged) grows
634 * the driver model tree.
636 * As a rule, SPI devices can't be probed. Instead, board init code
637 * provides a table listing the devices which are present, with enough
638 * information to bind and set up the device's driver. There's basic
639 * support for nonstatic configurations too; enough to handle adding
640 * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
643 /* board-specific information about each SPI device */
644 struct spi_board_info {
645 /* the device name and module name are coupled, like platform_bus;
646 * "modalias" is normally the driver name.
648 * platform_data goes to spi_device.dev.platform_data,
649 * controller_data goes to spi_device.controller_data,
652 char modalias[KOBJ_NAME_LEN];
653 const void *platform_data;
654 void *controller_data;
657 /* slower signaling on noisy or low voltage boards */
661 /* bus_num is board specific and matches the bus_num of some
662 * spi_master that will probably be registered later.
664 * chip_select reflects how this chip is wired to that master;
665 * it's less than num_chipselect.
670 /* mode becomes spi_device.mode, and is essential for chips
671 * where the default of SPI_CS_HIGH = 0 is wrong.
675 /* ... may need additional spi_device chip config data here.
676 * avoid stuff protocol drivers can set; but include stuff
677 * needed to behave without being bound to a driver:
678 * - quirks like clock rate mattering when not selected
684 spi_register_board_info(struct spi_board_info const *info, unsigned n);
686 /* board init code may ignore whether SPI is configured or not */
688 spi_register_board_info(struct spi_board_info const *info, unsigned n)
693 /* If you're hotplugging an adapter with devices (parport, usb, etc)
694 * use spi_new_device() to describe each device. You can also call
695 * spi_unregister_device() to start making that device vanish, but
696 * normally that would be handled by spi_unregister_master().
698 extern struct spi_device *
699 spi_new_device(struct spi_master *, struct spi_board_info *);
702 spi_unregister_device(struct spi_device *spi)
705 device_unregister(&spi->dev);
708 #endif /* __LINUX_SPI_H */