2 /* Common Flash Interface structures
3 * See http://support.intel.com/design/flash/technote/index.htm
4 * $Id: cfi.h,v 1.53 2005/03/15 19:03:13 gleixner Exp $
10 #include <linux/config.h>
11 #include <linux/version.h>
12 #include <linux/delay.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/mtd/flashchip.h>
16 #include <linux/mtd/map.h>
17 #include <linux/mtd/cfi_endian.h>
19 #ifdef CONFIG_MTD_CFI_I1
20 #define cfi_interleave(cfi) 1
21 #define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
23 #define cfi_interleave_is_1(cfi) (0)
26 #ifdef CONFIG_MTD_CFI_I2
27 # ifdef cfi_interleave
28 # undef cfi_interleave
29 # define cfi_interleave(cfi) ((cfi)->interleave)
31 # define cfi_interleave(cfi) 2
33 #define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
35 #define cfi_interleave_is_2(cfi) (0)
38 #ifdef CONFIG_MTD_CFI_I4
39 # ifdef cfi_interleave
40 # undef cfi_interleave
41 # define cfi_interleave(cfi) ((cfi)->interleave)
43 # define cfi_interleave(cfi) 4
45 #define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
47 #define cfi_interleave_is_4(cfi) (0)
50 #ifdef CONFIG_MTD_CFI_I8
51 # ifdef cfi_interleave
52 # undef cfi_interleave
53 # define cfi_interleave(cfi) ((cfi)->interleave)
55 # define cfi_interleave(cfi) 8
57 #define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
59 #define cfi_interleave_is_8(cfi) (0)
62 static inline int cfi_interleave_supported(int i)
65 #ifdef CONFIG_MTD_CFI_I1
68 #ifdef CONFIG_MTD_CFI_I2
71 #ifdef CONFIG_MTD_CFI_I4
74 #ifdef CONFIG_MTD_CFI_I8
85 /* NB: these values must represents the number of bytes needed to meet the
86 * device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes.
87 * These numbers are used in calculations.
89 #define CFI_DEVICETYPE_X8 (8 / 8)
90 #define CFI_DEVICETYPE_X16 (16 / 8)
91 #define CFI_DEVICETYPE_X32 (32 / 8)
92 #define CFI_DEVICETYPE_X64 (64 / 8)
94 /* NB: We keep these structures in memory in HOST byteorder, except
95 * where individually noted.
98 /* Basic Query Structure */
109 uint8_t WordWriteTimeoutTyp;
110 uint8_t BufWriteTimeoutTyp;
111 uint8_t BlockEraseTimeoutTyp;
112 uint8_t ChipEraseTimeoutTyp;
113 uint8_t WordWriteTimeoutMax;
114 uint8_t BufWriteTimeoutMax;
115 uint8_t BlockEraseTimeoutMax;
116 uint8_t ChipEraseTimeoutMax;
118 uint16_t InterfaceDesc;
119 uint16_t MaxBufWriteSize;
120 uint8_t NumEraseRegions;
121 uint32_t EraseRegionInfo[0]; /* Not host ordered */
122 } __attribute__((packed));
124 /* Extended Query Structure for both PRI and ALT */
126 struct cfi_extquery {
128 uint8_t MajorVersion;
129 uint8_t MinorVersion;
130 } __attribute__((packed));
132 /* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
134 struct cfi_pri_intelext {
136 uint8_t MajorVersion;
137 uint8_t MinorVersion;
138 uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
139 block follows - FIXME - not currently supported */
140 uint8_t SuspendCmdSupport;
141 uint16_t BlkStatusRegMask;
144 uint8_t NumProtectionFields;
145 uint16_t ProtRegAddr;
146 uint8_t FactProtRegSize;
147 uint8_t UserProtRegSize;
149 } __attribute__((packed));
151 struct cfi_intelext_otpinfo {
152 uint32_t ProtRegAddr;
154 uint8_t FactProtRegSize;
156 uint8_t UserProtRegSize;
157 } __attribute__((packed));
159 struct cfi_intelext_blockinfo {
160 uint16_t NumIdentBlocks;
162 uint16_t MinBlockEraseCycles;
165 } __attribute__((packed));
167 struct cfi_intelext_regioninfo {
168 uint16_t NumIdentPartitions;
169 uint8_t NumOpAllowed;
170 uint8_t NumOpAllowedSimProgMode;
171 uint8_t NumOpAllowedSimEraMode;
172 uint8_t NumBlockTypes;
173 struct cfi_intelext_blockinfo BlockTypes[1];
174 } __attribute__((packed));
176 /* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
178 struct cfi_pri_amdstd {
180 uint8_t MajorVersion;
181 uint8_t MinorVersion;
182 uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
183 uint8_t EraseSuspend;
185 uint8_t TmpBlkUnprotect;
186 uint8_t BlkProtUnprot;
187 uint8_t SimultaneousOps;
193 } __attribute__((packed));
195 struct cfi_pri_query {
197 uint32_t ProtField[1]; /* Not host ordered */
198 } __attribute__((packed));
200 struct cfi_bri_query {
201 uint8_t PageModeReadCap;
203 uint32_t ConfField[1]; /* Not host ordered */
204 } __attribute__((packed));
206 #define P_ID_NONE 0x0000
207 #define P_ID_INTEL_EXT 0x0001
208 #define P_ID_AMD_STD 0x0002
209 #define P_ID_INTEL_STD 0x0003
210 #define P_ID_AMD_EXT 0x0004
211 #define P_ID_WINBOND 0x0006
212 #define P_ID_ST_ADV 0x0020
213 #define P_ID_MITSUBISHI_STD 0x0100
214 #define P_ID_MITSUBISHI_EXT 0x0101
215 #define P_ID_SST_PAGE 0x0102
216 #define P_ID_INTEL_PERFORMANCE 0x0200
217 #define P_ID_INTEL_DATA 0x0210
218 #define P_ID_RESERVED 0xffff
221 #define CFI_MODE_CFI 1
222 #define CFI_MODE_JEDEC 0
229 int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */
232 struct mtd_info *(*cmdset_setup)(struct map_info *);
233 struct cfi_ident *cfiq; /* For now only one. We insist that all devs
234 must be of the same type. */
237 unsigned long chipshift; /* Because they're of the same type */
238 const char *im_name; /* inter_module name for cmdset_setup */
239 struct flchip chips[0]; /* per-chip data structure for each chip */
243 * Returns the command address according to the given geometry.
245 static inline uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs, int interleave, int type)
247 return (cmd_ofs * type) * interleave;
251 * Transforms the CFI command for the given geometry (bus width & interleave).
252 * It looks too long to be inline, but in the common case it should almost all
253 * get optimised away.
255 static inline map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi)
257 map_word val = { {0} };
258 int wordwidth, words_per_bus, chip_mode, chips_per_word;
259 unsigned long onecmd;
262 /* We do it this way to give the compiler a fighting chance
263 of optimising away all the crap for 'bankwidth' larger than
264 an unsigned long, in the common case where that support is
266 if (map_bankwidth_is_large(map)) {
267 wordwidth = sizeof(unsigned long);
268 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
270 wordwidth = map_bankwidth(map);
274 chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
275 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
277 /* First, determine what the bit-pattern should be for a single
278 device, according to chip mode and endianness... */
285 onecmd = cpu_to_cfi16(cmd);
288 onecmd = cpu_to_cfi32(cmd);
292 /* Now replicate it across the size of an unsigned long, or
293 just to the bus width as appropriate */
294 switch (chips_per_word) {
296 #if BITS_PER_LONG >= 64
298 onecmd |= (onecmd << (chip_mode * 32));
301 onecmd |= (onecmd << (chip_mode * 16));
303 onecmd |= (onecmd << (chip_mode * 8));
308 /* And finally, for the multi-word case, replicate it
309 in all words in the structure */
310 for (i=0; i < words_per_bus; i++) {
316 #define CMD(x) cfi_build_cmd((x), map, cfi)
319 static inline unsigned char cfi_merge_status(map_word val, struct map_info *map,
320 struct cfi_private *cfi)
322 int wordwidth, words_per_bus, chip_mode, chips_per_word;
323 unsigned long onestat, res = 0;
326 /* We do it this way to give the compiler a fighting chance
327 of optimising away all the crap for 'bankwidth' larger than
328 an unsigned long, in the common case where that support is
330 if (map_bankwidth_is_large(map)) {
331 wordwidth = sizeof(unsigned long);
332 words_per_bus = (map_bankwidth(map)) / wordwidth; // i.e. normally 1
334 wordwidth = map_bankwidth(map);
338 chip_mode = map_bankwidth(map) / cfi_interleave(cfi);
339 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map);
342 /* Or all status words together */
343 for (i=1; i < words_per_bus; i++) {
348 switch(chips_per_word) {
350 #if BITS_PER_LONG >= 64
352 res |= (onestat >> (chip_mode * 32));
355 res |= (onestat >> (chip_mode * 16));
357 res |= (onestat >> (chip_mode * 8));
362 /* Last, determine what the bit-pattern should be for a single
363 device, according to chip mode and endianness... */
368 res = cfi16_to_cpu(res);
371 res = cfi32_to_cpu(res);
378 #define MERGESTATUS(x) cfi_merge_status((x), map, cfi)
382 * Sends a CFI command to a bank of flash for the given geometry.
384 * Returns the offset in flash where the command was written.
385 * If prev_val is non-null, it will be set to the value at the command address,
386 * before the command was written.
388 static inline uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
389 struct map_info *map, struct cfi_private *cfi,
390 int type, map_word *prev_val)
393 uint32_t addr = base + cfi_build_cmd_addr(cmd_addr, cfi_interleave(cfi), type);
395 val = cfi_build_cmd(cmd, map, cfi);
398 *prev_val = map_read(map, addr);
400 map_write(map, val, addr);
405 static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
407 map_word val = map_read(map, addr);
409 if (map_bankwidth_is_1(map)) {
411 } else if (map_bankwidth_is_2(map)) {
412 return cfi16_to_cpu(val.x[0]);
414 /* No point in a 64-bit byteswap since that would just be
415 swapping the responses from different chips, and we are
416 only interested in one chip (a representative sample) */
417 return cfi32_to_cpu(val.x[0]);
421 static inline void cfi_udelay(int us)
424 msleep((us+999)/1000);
431 static inline void cfi_spin_lock(spinlock_t *mutex)
436 static inline void cfi_spin_unlock(spinlock_t *mutex)
438 spin_unlock_bh(mutex);
441 struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
446 void (*fixup)(struct mtd_info *mtd, void* param);
450 #define CFI_MFR_ANY 0xffff
451 #define CFI_ID_ANY 0xffff
453 #define CFI_MFR_AMD 0x0001
454 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */
456 void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups);
458 typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip,
459 unsigned long adr, int len, void *thunk);
461 int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
462 loff_t ofs, size_t len, void *thunk);
465 #endif /* __MTD_CFI_H__ */