5 * We need the APIC definitions automatically as part of 'smp.h'
8 #include <linux/config.h>
9 #include <linux/threads.h>
10 #include <linux/cpumask.h>
11 #include <linux/bitops.h>
12 extern int disable_apic;
15 #ifdef CONFIG_X86_LOCAL_APIC
17 #include <asm/fixmap.h>
18 #include <asm/mpspec.h>
19 #ifdef CONFIG_X86_IO_APIC
20 #include <asm/io_apic.h>
23 #include <asm/thread_info.h>
35 * Private routines/data
38 extern void smp_alloc_memory(void);
39 extern cpumask_t cpu_online_map;
40 extern volatile unsigned long smp_invalidate_needed;
42 extern int smp_num_siblings;
43 extern void smp_flush_tlb(void);
44 extern void smp_message_irq(int cpl, void *dev_id, struct pt_regs *regs);
45 extern void smp_send_reschedule(int cpu);
46 extern void smp_invalidate_rcv(void); /* Process an NMI */
47 extern void (*mtrr_hook) (void);
48 extern void zap_low_mappings(void);
49 void smp_stop_cpu(void);
50 extern cpumask_t cpu_sibling_map[NR_CPUS];
51 extern cpumask_t cpu_core_map[NR_CPUS];
52 extern u8 phys_proc_id[NR_CPUS];
53 extern u8 cpu_core_id[NR_CPUS];
55 #define SMP_TRAMPOLINE_BASE 0x6000
58 * On x86 all CPUs are mapped 1:1 to the APIC space.
59 * This simplifies scheduling and IPI sending and
60 * compresses data structures.
63 extern cpumask_t cpu_callout_map;
64 extern cpumask_t cpu_callin_map;
65 #define cpu_possible_map cpu_callout_map
67 static inline int num_booting_cpus(void)
69 return cpus_weight(cpu_callout_map);
72 #define __smp_processor_id() read_pda(cpunumber)
74 extern __inline int hard_smp_processor_id(void)
76 /* we don't want to mark this access volatile - bad code generation */
77 return GET_APIC_ID(*(unsigned int *)(APIC_BASE+APIC_ID));
80 #define safe_smp_processor_id() (disable_apic ? 0 : x86_apicid_to_cpu(hard_smp_processor_id()))
82 #endif /* !ASSEMBLY */
84 #define NO_PROC_ID 0xFF /* No processor magic marker */
90 * Some lowlevel functions might want to know about
91 * the real APIC ID <-> CPU # mapping.
93 extern u8 x86_cpu_to_apicid[NR_CPUS]; /* physical ID */
94 extern u8 x86_cpu_to_log_apicid[NR_CPUS];
95 extern u8 bios_cpu_apicid[];
97 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
99 return cpus_addr(cpumask)[0];
102 static inline int x86_apicid_to_cpu(u8 apicid)
106 for (i = 0; i < NR_CPUS; ++i)
107 if (x86_cpu_to_apicid[i] == apicid)
110 /* No entries in x86_cpu_to_apicid? Either no MPS|ACPI,
111 * or called too early. Either way, we must be CPU 0. */
112 if (x86_cpu_to_apicid[0] == BAD_APICID)
118 static inline int cpu_present_to_apicid(int mps_cpu)
120 if (mps_cpu < NR_CPUS)
121 return (int)bios_cpu_apicid[mps_cpu];
126 #endif /* !ASSEMBLY */
129 #define stack_smp_processor_id() 0
130 #define safe_smp_processor_id() 0
131 #define cpu_logical_map(x) (x)
133 #include <asm/thread_info.h>
134 #define stack_smp_processor_id() \
136 struct thread_info *ti; \
137 __asm__("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
143 static __inline int logical_smp_processor_id(void)
145 /* we don't want to mark this access volatile - bad code generation */
146 return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));