err.no Git - linux-2.6/blob - include/asm-x86/system.h

   1 #ifndef _ASM_X86_SYSTEM_H_
   2 #define _ASM_X86_SYSTEM_H_
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8
   9 #include <linux/kernel.h>
  10 #include <linux/irqflags.h>
  11
  12 #ifdef CONFIG_X86_32
  13 #define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
  14
  15 struct task_struct; /* one of the stranger aspects of C forward declarations */
  16 extern struct task_struct *FASTCALL(__switch_to(struct task_struct *prev,
  17                                                 struct task_struct *next));
  18
  19 /*
  20  * Saving eflags is important. It switches not only IOPL between tasks,
  21  * it also protects other tasks from NT leaking through sysenter etc.
  22  */
  23 #define switch_to(prev, next, last) do {                                \
  24         unsigned long esi, edi;                                         \
  25         asm volatile("pushfl\n\t"               /* Save flags */        \
  26                      "pushl %%ebp\n\t"                                  \
  27                      "movl %%esp,%0\n\t"        /* save ESP */          \
  28                      "movl %5,%%esp\n\t"        /* restore ESP */       \
  29                      "movl $1f,%1\n\t"          /* save EIP */          \
  30                      "pushl %6\n\t"             /* restore EIP */       \
  31                      "jmp __switch_to\n"                                \
  32                      "1:\t"                                             \
  33                      "popl %%ebp\n\t"                                   \
  34                      "popfl"                                            \
  35                      :"=m" (prev->thread.sp), "=m" (prev->thread.ip),   \
  36                       "=a" (last), "=S" (esi), "=D" (edi)               \
  37                      :"m" (next->thread.sp), "m" (next->thread.ip),     \
  38                       "2" (prev), "d" (next));                          \
  39 } while (0)
  40
  41 /*
  42  * disable hlt during certain critical i/o operations
  43  */
  44 #define HAVE_DISABLE_HLT
  45 #else
  46 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  47 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  48
  49 /* frame pointer must be last for get_wchan */
  50 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  51 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  52
  53 #define __EXTRA_CLOBBER  \
  54         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
  55           "r12", "r13", "r14", "r15"
  56
  57 /* Save restore flags to clear handle leaking NT */
  58 #define switch_to(prev, next, last) \
  59         asm volatile(SAVE_CONTEXT                                         \
  60              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  61              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  62              "call __switch_to\n\t"                                       \
  63              ".globl thread_return\n"                                     \
  64              "thread_return:\n\t"                                         \
  65              "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  66              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  67              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
  68              "movq %%rax,%%rdi\n\t"                                       \
  69              "jc   ret_from_fork\n\t"                                     \
  70              RESTORE_CONTEXT                                              \
  71              : "=a" (last)                                                \
  72              : [next] "S" (next), [prev] "D" (prev),                      \
  73                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
  74                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
  75                [tif_fork] "i" (TIF_FORK),                                 \
  76                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
  77                [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))  \
  78              : "memory", "cc" __EXTRA_CLOBBER)
  79 #endif
  80
  81 #ifdef __KERNEL__
  82 #define _set_base(addr, base) do { unsigned long __pr; \
  83 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  84         "rorl $16,%%edx\n\t" \
  85         "movb %%dl,%2\n\t" \
  86         "movb %%dh,%3" \
  87         :"=&d" (__pr) \
  88         :"m" (*((addr)+2)), \
  89          "m" (*((addr)+4)), \
  90          "m" (*((addr)+7)), \
  91          "0" (base) \
  92         ); } while (0)
  93
  94 #define _set_limit(addr, limit) do { unsigned long __lr; \
  95 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
  96         "rorl $16,%%edx\n\t" \
  97         "movb %2,%%dh\n\t" \
  98         "andb $0xf0,%%dh\n\t" \
  99         "orb %%dh,%%dl\n\t" \
 100         "movb %%dl,%2" \
 101         :"=&d" (__lr) \
 102         :"m" (*(addr)), \
 103          "m" (*((addr)+6)), \
 104          "0" (limit) \
 105         ); } while (0)
 106
 107 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 108 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 109
 110 extern void load_gs_index(unsigned);
 111
 112 /*
 113  * Load a segment. Fall back on loading the zero
 114  * segment if something goes wrong..
 115  */
 116 #define loadsegment(seg, value)                 \
 117         asm volatile("\n"                       \
 118                 "1:\t"                          \
 119                 "movl %k0,%%" #seg "\n"         \
 120                 "2:\n"                          \
 121                 ".section .fixup,\"ax\"\n"      \
 122                 "3:\t"                          \
 123                 "movl %k1, %%" #seg "\n\t"      \
 124                 "jmp 2b\n"                      \
 125                 ".previous\n"                   \
 126                 ".section __ex_table,\"a\"\n\t" \
 127                 _ASM_ALIGN "\n\t"               \
 128                 _ASM_PTR " 1b,3b\n"             \
 129                 ".previous"                     \
 130                 : :"r" (value), "r" (0))
 131
 132
 133 /*
 134  * Save a segment register away
 135  */
 136 #define savesegment(seg, value) \
 137         asm volatile("mov %%" #seg ",%0":"=rm" (value))
 138
 139 static inline unsigned long get_limit(unsigned long segment)
 140 {
 141         unsigned long __limit;
 142         __asm__("lsll %1,%0"
 143                 :"=r" (__limit):"r" (segment));
 144         return __limit+1;
 145 }
 146
 147 static inline void native_clts(void)
 148 {
 149         asm volatile ("clts");
 150 }
 151
 152 /*
 153  * Volatile isn't enough to prevent the compiler from reordering the
 154  * read/write functions for the control registers and messing everything up.
 155  * A memory clobber would solve the problem, but would prevent reordering of
 156  * all loads stores around it, which can hurt performance. Solution is to
 157  * use a variable and mimic reads and writes to it to enforce serialization
 158  */
 159 static unsigned long __force_order;
 160
 161 static inline unsigned long native_read_cr0(void)
 162 {
 163         unsigned long val;
 164         asm volatile("mov %%cr0,%0\n\t" :"=r" (val), "=m" (__force_order));
 165         return val;
 166 }
 167
 168 static inline void native_write_cr0(unsigned long val)
 169 {
 170         asm volatile("mov %0,%%cr0": :"r" (val), "m" (__force_order));
 171 }
 172
 173 static inline unsigned long native_read_cr2(void)
 174 {
 175         unsigned long val;
 176         asm volatile("mov %%cr2,%0\n\t" :"=r" (val), "=m" (__force_order));
 177         return val;
 178 }
 179
 180 static inline void native_write_cr2(unsigned long val)
 181 {
 182         asm volatile("mov %0,%%cr2": :"r" (val), "m" (__force_order));
 183 }
 184
 185 static inline unsigned long native_read_cr3(void)
 186 {
 187         unsigned long val;
 188         asm volatile("mov %%cr3,%0\n\t" :"=r" (val), "=m" (__force_order));
 189         return val;
 190 }
 191
 192 static inline void native_write_cr3(unsigned long val)
 193 {
 194         asm volatile("mov %0,%%cr3": :"r" (val), "m" (__force_order));
 195 }
 196
 197 static inline unsigned long native_read_cr4(void)
 198 {
 199         unsigned long val;
 200         asm volatile("mov %%cr4,%0\n\t" :"=r" (val), "=m" (__force_order));
 201         return val;
 202 }
 203
 204 static inline unsigned long native_read_cr4_safe(void)
 205 {
 206         unsigned long val;
 207         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 208          * exists, so it will never fail. */
 209 #ifdef CONFIG_X86_32
 210         asm volatile("1: mov %%cr4, %0          \n"
 211                 "2:                             \n"
 212                 ".section __ex_table,\"a\"      \n"
 213                 ".long 1b,2b                    \n"
 214                 ".previous                      \n"
 215                 : "=r" (val), "=m" (__force_order) : "0" (0));
 216 #else
 217         val = native_read_cr4();
 218 #endif
 219         return val;
 220 }
 221
 222 static inline void native_write_cr4(unsigned long val)
 223 {
 224         asm volatile("mov %0,%%cr4": :"r" (val), "m" (__force_order));
 225 }
 226
 227 static inline void native_wbinvd(void)
 228 {
 229         asm volatile("wbinvd": : :"memory");
 230 }
 231 #ifdef CONFIG_PARAVIRT
 232 #include <asm/paravirt.h>
 233 #else
 234 #define read_cr0()      (native_read_cr0())
 235 #define write_cr0(x)    (native_write_cr0(x))
 236 #define read_cr2()      (native_read_cr2())
 237 #define write_cr2(x)    (native_write_cr2(x))
 238 #define read_cr3()      (native_read_cr3())
 239 #define write_cr3(x)    (native_write_cr3(x))
 240 #define read_cr4()      (native_read_cr4())
 241 #define read_cr4_safe() (native_read_cr4_safe())
 242 #define write_cr4(x)    (native_write_cr4(x))
 243 #define wbinvd()        (native_wbinvd())
 244
 245 #ifdef CONFIG_X86_64
 246
 247 static inline unsigned long read_cr8(void)
 248 {
 249         unsigned long cr8;
 250         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 251         return cr8;
 252 }
 253
 254 static inline void write_cr8(unsigned long val)
 255 {
 256         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 257 }
 258
 259 #endif
 260
 261 /* Clear the 'TS' bit */
 262 #define clts()          (native_clts())
 263
 264 #endif/* CONFIG_PARAVIRT */
 265
 266 #define stts() write_cr0(8 | read_cr0())
 267
 268 #endif /* __KERNEL__ */
 269
 270 static inline void clflush(void *__p)
 271 {
 272         asm volatile("clflush %0" : "+m" (*(char __force *)__p));
 273 }
 274
 275 #define nop() __asm__ __volatile__ ("nop")
 276
 277 void disable_hlt(void);
 278 void enable_hlt(void);
 279
 280 extern int es7000_plat;
 281 void cpu_idle_wait(void);
 282
 283 extern unsigned long arch_align_stack(unsigned long sp);
 284 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 285
 286 void default_idle(void);
 287
 288 /*
 289  * Force strict CPU ordering.
 290  * And yes, this is required on UP too when we're talking
 291  * to devices.
 292  */
 293 #ifdef CONFIG_X86_32
 294 /*
 295  * For now, "wmb()" doesn't actually do anything, as all
 296  * Intel CPU's follow what Intel calls a *Processor Order*,
 297  * in which all writes are seen in the program order even
 298  * outside the CPU.
 299  *
 300  * I expect future Intel CPU's to have a weaker ordering,
 301  * but I'd also expect them to finally get their act together
 302  * and add some real memory barriers if so.
 303  *
 304  * Some non intel clones support out of order store. wmb() ceases to be a
 305  * nop for these.
 306  */
 307 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 308 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 309 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 310 #else
 311 #define mb()    asm volatile("mfence":::"memory")
 312 #define rmb()   asm volatile("lfence":::"memory")
 313 #define wmb()   asm volatile("sfence" ::: "memory")
 314 #endif
 315
 316 /**
 317  * read_barrier_depends - Flush all pending reads that subsequents reads
 318  * depend on.
 319  *
 320  * No data-dependent reads from memory-like regions are ever reordered
 321  * over this barrier.  All reads preceding this primitive are guaranteed
 322  * to access memory (but not necessarily other CPUs' caches) before any
 323  * reads following this primitive that depend on the data return by
 324  * any of the preceding reads.  This primitive is much lighter weight than
 325  * rmb() on most CPUs, and is never heavier weight than is
 326  * rmb().
 327  *
 328  * These ordering constraints are respected by both the local CPU
 329  * and the compiler.
 330  *
 331  * Ordering is not guaranteed by anything other than these primitives,
 332  * not even by data dependencies.  See the documentation for
 333  * memory_barrier() for examples and URLs to more information.
 334  *
 335  * For example, the following code would force ordering (the initial
 336  * value of "a" is zero, "b" is one, and "p" is "&a"):
 337  *
 338  * <programlisting>
 339  *      CPU 0                           CPU 1
 340  *
 341  *      b = 2;
 342  *      memory_barrier();
 343  *      p = &b;                         q = p;
 344  *                                      read_barrier_depends();
 345  *                                      d = *q;
 346  * </programlisting>
 347  *
 348  * because the read of "*q" depends on the read of "p" and these
 349  * two reads are separated by a read_barrier_depends().  However,
 350  * the following code, with the same initial values for "a" and "b":
 351  *
 352  * <programlisting>
 353  *      CPU 0                           CPU 1
 354  *
 355  *      a = 2;
 356  *      memory_barrier();
 357  *      b = 3;                          y = b;
 358  *                                      read_barrier_depends();
 359  *                                      x = a;
 360  * </programlisting>
 361  *
 362  * does not enforce ordering, since there is no data dependency between
 363  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 364  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 365  * in cases like this where there are no data dependencies.
 366  **/
 367
 368 #define read_barrier_depends()  do { } while (0)
 369
 370 #ifdef CONFIG_SMP
 371 #define smp_mb()        mb()
 372 #ifdef CONFIG_X86_PPRO_FENCE
 373 # define smp_rmb()      rmb()
 374 #else
 375 # define smp_rmb()      barrier()
 376 #endif
 377 #ifdef CONFIG_X86_OOSTORE
 378 # define smp_wmb()      wmb()
 379 #else
 380 # define smp_wmb()      barrier()
 381 #endif
 382 #define smp_read_barrier_depends()      read_barrier_depends()
 383 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 384 #else
 385 #define smp_mb()        barrier()
 386 #define smp_rmb()       barrier()
 387 #define smp_wmb()       barrier()
 388 #define smp_read_barrier_depends()      do { } while (0)
 389 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 390 #endif
 391
 392
 393 #endif