2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_I386_PROCESSOR_H
6 #define __ASM_I386_PROCESSOR_H
9 #include <asm/math_emu.h>
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
16 #include <asm/system.h>
17 #include <linux/cache.h>
18 #include <linux/threads.h>
19 #include <asm/percpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/init.h>
22 #include <asm/processor-flags.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 static inline int desc_empty(const void *ptr)
33 const u32 *desc = ptr;
34 return !(desc[0] | desc[1]);
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
41 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
64 int x86_cache_alignment; /* In bytes */
70 unsigned long loops_per_jiffy;
72 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
74 unsigned char x86_max_cores; /* cpuid returned max cores value */
76 unsigned short x86_clflush_size;
78 unsigned char booted_cores; /* number of cores as seen by OS */
79 __u8 phys_proc_id; /* Physical processor id. */
80 __u8 cpu_core_id; /* Core id */
81 __u8 cpu_index; /* index into per_cpu list */
83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
85 #define X86_VENDOR_INTEL 0
86 #define X86_VENDOR_CYRIX 1
87 #define X86_VENDOR_AMD 2
88 #define X86_VENDOR_UMC 3
89 #define X86_VENDOR_NEXGEN 4
90 #define X86_VENDOR_CENTAUR 5
91 #define X86_VENDOR_TRANSMETA 7
92 #define X86_VENDOR_NSC 8
93 #define X86_VENDOR_NUM 9
94 #define X86_VENDOR_UNKNOWN 0xff
97 * capabilities of CPUs
100 extern struct cpuinfo_x86 boot_cpu_data;
101 extern struct cpuinfo_x86 new_cpu_data;
102 extern struct tss_struct doublefault_tss;
103 DECLARE_PER_CPU(struct tss_struct, init_tss);
106 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
107 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
108 #define current_cpu_data cpu_data(smp_processor_id())
110 #define cpu_data(cpu) boot_cpu_data
111 #define current_cpu_data boot_cpu_data
115 * the following now lives in the per cpu area:
116 * extern int cpu_llc_id[NR_CPUS];
118 DECLARE_PER_CPU(u8, cpu_llc_id);
119 extern char ignore_fpu_irq;
121 void __init cpu_detect(struct cpuinfo_x86 *c);
123 extern void identify_boot_cpu(void);
124 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
125 extern void print_cpu_info(struct cpuinfo_x86 *);
126 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
127 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
128 extern unsigned short num_cache_leaves;
131 extern void detect_ht(struct cpuinfo_x86 *c);
133 static inline void detect_ht(struct cpuinfo_x86 *c) {}
136 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
139 * Save the cr4 feature set we're using (ie
140 * Pentium 4MB enable and PPro Global page
141 * enable), so that any CPU's that boot up
142 * after us can get the correct flags.
144 extern unsigned long mmu_cr4_features;
146 static inline void set_in_cr4 (unsigned long mask)
149 mmu_cr4_features |= mask;
155 static inline void clear_in_cr4 (unsigned long mask)
158 mmu_cr4_features &= ~mask;
164 /* Stop speculative execution */
165 static inline void sync_core(void)
168 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
171 static inline void __monitor(const void *eax, unsigned long ecx,
174 /* "monitor %eax,%ecx,%edx;" */
176 ".byte 0x0f,0x01,0xc8;"
177 : :"a" (eax), "c" (ecx), "d"(edx));
180 static inline void __mwait(unsigned long eax, unsigned long ecx)
182 /* "mwait %eax,%ecx;" */
184 ".byte 0x0f,0x01,0xc9;"
185 : :"a" (eax), "c" (ecx));
188 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
190 /* from system description table in BIOS. Mostly for MCA use, but
191 others may find it useful. */
192 extern unsigned int machine_id;
193 extern unsigned int machine_submodel_id;
194 extern unsigned int BIOS_revision;
195 extern unsigned int mca_pentium_flag;
197 /* Boot loader type from the setup header */
198 extern int bootloader_type;
201 * User space process size: 3GB (default).
203 #define TASK_SIZE (PAGE_OFFSET)
205 /* This decides where the kernel will search for a free chunk of vm
206 * space during mmap's.
208 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
210 #define HAVE_ARCH_PICK_MMAP_LAYOUT
212 extern void hard_disable_TSC(void);
213 extern void disable_TSC(void);
214 extern void hard_enable_TSC(void);
219 #define IO_BITMAP_BITS 65536
220 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
221 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
222 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
223 #define INVALID_IO_BITMAP_OFFSET 0x8000
224 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
226 struct i387_fsave_struct {
234 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
235 long status; /* software status information */
238 struct i387_fxsave_struct {
249 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
250 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
252 } __attribute__ ((aligned (16)));
254 struct i387_soft_struct {
262 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
263 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
265 unsigned long entry_eip;
269 struct i387_fsave_struct fsave;
270 struct i387_fxsave_struct fxsave;
271 struct i387_soft_struct soft;
278 struct thread_struct;
280 /* This is the TSS defined by the hardware. */
282 unsigned short back_link,__blh;
284 unsigned short ss0,__ss0h;
286 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
288 unsigned short ss2,__ss2h;
292 unsigned long ax, cx, dx, bx;
293 unsigned long sp, bp, si, di;
294 unsigned short es, __esh;
295 unsigned short cs, __csh;
296 unsigned short ss, __ssh;
297 unsigned short ds, __dsh;
298 unsigned short fs, __fsh;
299 unsigned short gs, __gsh;
300 unsigned short ldt, __ldth;
301 unsigned short trace, io_bitmap_base;
302 } __attribute__((packed));
305 struct i386_hw_tss x86_tss;
308 * The extra 1 is there because the CPU will access an
309 * additional byte beyond the end of the IO permission
310 * bitmap. The extra byte must be all 1 bits, and must
311 * be within the limit.
313 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
315 * Cache the current maximum and the last task that used the bitmap:
317 unsigned long io_bitmap_max;
318 struct thread_struct *io_bitmap_owner;
320 * pads the TSS to be cacheline-aligned (size is 0x100)
322 unsigned long __cacheline_filler[35];
324 * .. and then another 0x100 bytes for emergency kernel stack
326 unsigned long stack[64];
327 } __attribute__((packed));
329 #define ARCH_MIN_TASKALIGN 16
331 struct thread_struct {
332 /* cached TLS descriptors. */
333 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
335 unsigned long sysenter_cs;
340 /* Hardware debugging registers */
341 unsigned long debugreg0;
342 unsigned long debugreg1;
343 unsigned long debugreg2;
344 unsigned long debugreg3;
345 unsigned long debugreg6;
346 unsigned long debugreg7;
348 unsigned long cr2, trap_no, error_code;
349 /* floating point info */
350 union i387_union i387;
351 /* virtual 86 mode info */
352 struct vm86_struct __user * vm86_info;
353 unsigned long screen_bitmap;
354 unsigned long v86flags, v86mask, saved_sp0;
355 unsigned int saved_fs, saved_gs;
357 unsigned long *io_bitmap_ptr;
359 /* max allowed port in the bitmap, in bytes: */
360 unsigned long io_bitmap_max;
361 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
362 unsigned long debugctlmsr;
363 /* Debug Store - if not 0 points to a DS Save Area configuration;
364 * goes into MSR_IA32_DS_AREA */
365 unsigned long ds_area_msr;
368 #define INIT_THREAD { \
369 .sp0 = sizeof(init_stack) + (long)&init_stack, \
371 .sysenter_cs = __KERNEL_CS, \
372 .io_bitmap_ptr = NULL, \
373 .fs = __KERNEL_PERCPU, \
377 * Note that the .io_bitmap member must be extra-big. This is because
378 * the CPU will access an additional byte beyond the end of the IO
379 * permission bitmap. The extra byte must be all 1 bits, and must
380 * be within the limit.
384 .sp0 = sizeof(init_stack) + (long)&init_stack, \
385 .ss0 = __KERNEL_DS, \
386 .ss1 = __KERNEL_CS, \
387 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
389 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
392 #define start_thread(regs, new_eip, new_esp) do { \
393 __asm__("movl %0,%%gs": :"r" (0)); \
396 regs->ds = __USER_DS; \
397 regs->es = __USER_DS; \
398 regs->ss = __USER_DS; \
399 regs->cs = __USER_CS; \
400 regs->ip = new_eip; \
401 regs->sp = new_esp; \
404 /* Forward declaration, a strange C thing */
408 /* Free all resources held by a thread. */
409 extern void release_thread(struct task_struct *);
411 /* Prepare to copy thread state - unlazy all lazy status */
412 extern void prepare_to_copy(struct task_struct *tsk);
415 * create a kernel thread without removing it from tasklists
417 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
419 extern unsigned long thread_saved_pc(struct task_struct *tsk);
421 unsigned long get_wchan(struct task_struct *p);
423 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
424 #define KSTK_TOP(info) \
426 unsigned long *__ptr = (unsigned long *)(info); \
427 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
431 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
432 * This is necessary to guarantee that the entire "struct pt_regs"
433 * is accessable even if the CPU haven't stored the SS/ESP registers
434 * on the stack (interrupt gate does not save these registers
435 * when switching to the same priv ring).
436 * Therefore beware: accessing the ss/esp fields of the
437 * "struct pt_regs" is possible, but they may contain the
438 * completely wrong values.
440 #define task_pt_regs(task) \
442 struct pt_regs *__regs__; \
443 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
447 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
448 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
451 struct microcode_header {
459 unsigned int datasize;
460 unsigned int totalsize;
461 unsigned int reserved[3];
465 struct microcode_header hdr;
466 unsigned int bits[0];
469 typedef struct microcode microcode_t;
470 typedef struct microcode_header microcode_header_t;
472 /* microcode format is extended from prescott processors */
473 struct extended_signature {
479 struct extended_sigtable {
482 unsigned int reserved[3];
483 struct extended_signature sigs[0];
486 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
487 static inline void rep_nop(void)
489 __asm__ __volatile__("rep;nop": : :"memory");
492 #define cpu_relax() rep_nop()
494 static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
496 tss->x86_tss.sp0 = thread->sp0;
497 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
498 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
499 tss->x86_tss.ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
505 static inline unsigned long native_get_debugreg(int regno)
507 unsigned long val = 0; /* Damn you, gcc! */
511 asm("movl %%db0, %0" :"=r" (val)); break;
513 asm("movl %%db1, %0" :"=r" (val)); break;
515 asm("movl %%db2, %0" :"=r" (val)); break;
517 asm("movl %%db3, %0" :"=r" (val)); break;
519 asm("movl %%db6, %0" :"=r" (val)); break;
521 asm("movl %%db7, %0" :"=r" (val)); break;
528 static inline void native_set_debugreg(int regno, unsigned long value)
532 asm("movl %0,%%db0" : /* no output */ :"r" (value));
535 asm("movl %0,%%db1" : /* no output */ :"r" (value));
538 asm("movl %0,%%db2" : /* no output */ :"r" (value));
541 asm("movl %0,%%db3" : /* no output */ :"r" (value));
544 asm("movl %0,%%db6" : /* no output */ :"r" (value));
547 asm("movl %0,%%db7" : /* no output */ :"r" (value));
555 * Set IOPL bits in EFLAGS from given mask
557 static inline void native_set_iopl_mask(unsigned mask)
560 __asm__ __volatile__ ("pushfl;"
567 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
570 #ifdef CONFIG_PARAVIRT
571 #include <asm/paravirt.h>
573 #define paravirt_enabled() 0
575 static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
577 native_load_sp0(tss, thread);
581 * These special macros can be used to get or set a debugging register
583 #define get_debugreg(var, register) \
584 (var) = native_get_debugreg(register)
585 #define set_debugreg(value, register) \
586 native_set_debugreg(register, value)
588 #define set_iopl_mask native_set_iopl_mask
589 #endif /* CONFIG_PARAVIRT */
591 /* generic versions from gas */
592 #define GENERIC_NOP1 ".byte 0x90\n"
593 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
594 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
595 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
596 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
597 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
598 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
599 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
602 #define K8_NOP1 GENERIC_NOP1
603 #define K8_NOP2 ".byte 0x66,0x90\n"
604 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
605 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
606 #define K8_NOP5 K8_NOP3 K8_NOP2
607 #define K8_NOP6 K8_NOP3 K8_NOP3
608 #define K8_NOP7 K8_NOP4 K8_NOP3
609 #define K8_NOP8 K8_NOP4 K8_NOP4
612 /* uses eax dependencies (arbitary choice) */
613 #define K7_NOP1 GENERIC_NOP1
614 #define K7_NOP2 ".byte 0x8b,0xc0\n"
615 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
616 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
617 #define K7_NOP5 K7_NOP4 ASM_NOP1
618 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
619 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
620 #define K7_NOP8 K7_NOP7 ASM_NOP1
623 /* uses eax dependencies (Intel-recommended choice) */
624 #define P6_NOP1 GENERIC_NOP1
625 #define P6_NOP2 ".byte 0x66,0x90\n"
626 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
627 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
628 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
629 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
630 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
631 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
634 #define ASM_NOP1 K8_NOP1
635 #define ASM_NOP2 K8_NOP2
636 #define ASM_NOP3 K8_NOP3
637 #define ASM_NOP4 K8_NOP4
638 #define ASM_NOP5 K8_NOP5
639 #define ASM_NOP6 K8_NOP6
640 #define ASM_NOP7 K8_NOP7
641 #define ASM_NOP8 K8_NOP8
642 #elif defined(CONFIG_MK7)
643 #define ASM_NOP1 K7_NOP1
644 #define ASM_NOP2 K7_NOP2
645 #define ASM_NOP3 K7_NOP3
646 #define ASM_NOP4 K7_NOP4
647 #define ASM_NOP5 K7_NOP5
648 #define ASM_NOP6 K7_NOP6
649 #define ASM_NOP7 K7_NOP7
650 #define ASM_NOP8 K7_NOP8
651 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
652 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
653 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
654 #define ASM_NOP1 P6_NOP1
655 #define ASM_NOP2 P6_NOP2
656 #define ASM_NOP3 P6_NOP3
657 #define ASM_NOP4 P6_NOP4
658 #define ASM_NOP5 P6_NOP5
659 #define ASM_NOP6 P6_NOP6
660 #define ASM_NOP7 P6_NOP7
661 #define ASM_NOP8 P6_NOP8
663 #define ASM_NOP1 GENERIC_NOP1
664 #define ASM_NOP2 GENERIC_NOP2
665 #define ASM_NOP3 GENERIC_NOP3
666 #define ASM_NOP4 GENERIC_NOP4
667 #define ASM_NOP5 GENERIC_NOP5
668 #define ASM_NOP6 GENERIC_NOP6
669 #define ASM_NOP7 GENERIC_NOP7
670 #define ASM_NOP8 GENERIC_NOP8
673 #define ASM_NOP_MAX 8
675 /* Prefetch instructions for Pentium III and AMD Athlon */
676 /* It's not worth to care about 3dnow! prefetches for the K6
677 because they are microcoded there and very slow.
678 However we don't do prefetches for pre XP Athlons currently
679 That should be fixed. */
680 #define ARCH_HAS_PREFETCH
681 static inline void prefetch(const void *x)
683 alternative_input(ASM_NOP4,
689 #define ARCH_HAS_PREFETCH
690 #define ARCH_HAS_PREFETCHW
691 #define ARCH_HAS_SPINLOCK_PREFETCH
693 /* 3dnow! prefetch to get an exclusive cache line. Useful for
694 spinlocks to avoid one state transition in the cache coherency protocol. */
695 static inline void prefetchw(const void *x)
697 alternative_input(ASM_NOP4,
702 #define spin_lock_prefetch(x) prefetchw(x)
704 extern void select_idle_routine(const struct cpuinfo_x86 *c);
706 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
708 extern unsigned long boot_option_idle_override;
709 extern void enable_sep_cpu(void);
710 extern int sysenter_setup(void);
712 /* Defined in head.S */
713 extern struct Xgt_desc_struct early_gdt_descr;
715 extern void cpu_set_gdt(int);
716 extern void switch_to_new_gdt(void);
717 extern void cpu_init(void);
718 extern void init_gdt(int cpu);
720 extern int force_mwait;
722 #endif /* __ASM_I386_PROCESSOR_H */