2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_I386_PROCESSOR_H
6 #define __ASM_I386_PROCESSOR_H
9 #include <asm/math_emu.h>
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
16 #include <asm/system.h>
17 #include <linux/cache.h>
18 #include <linux/threads.h>
19 #include <asm/percpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/init.h>
22 #include <asm/desc_defs.h>
25 * CPU type and hardware bug flags. Kept separately for each CPU.
26 * Members of this structure are referenced in head.S, so think twice
27 * before touching them. [mj]
31 __u8 x86; /* CPU family */
32 __u8 x86_vendor; /* CPU vendor */
35 char wp_works_ok; /* It doesn't on 386's */
36 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
39 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
40 unsigned long x86_capability[NCAPINTS];
41 char x86_vendor_id[16];
42 char x86_model_id[64];
43 int x86_cache_size; /* in KB - valid for CPUS which support this
45 int x86_cache_alignment; /* In bytes */
51 unsigned long loops_per_jiffy;
53 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
55 unsigned char x86_max_cores; /* cpuid returned max cores value */
57 unsigned short x86_clflush_size;
59 unsigned char booted_cores; /* number of cores as seen by OS */
60 __u8 phys_proc_id; /* Physical processor id. */
61 __u8 cpu_core_id; /* Core id */
62 __u8 cpu_index; /* index into per_cpu list */
64 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
66 #define X86_VENDOR_INTEL 0
67 #define X86_VENDOR_CYRIX 1
68 #define X86_VENDOR_AMD 2
69 #define X86_VENDOR_UMC 3
70 #define X86_VENDOR_NEXGEN 4
71 #define X86_VENDOR_CENTAUR 5
72 #define X86_VENDOR_TRANSMETA 7
73 #define X86_VENDOR_NSC 8
74 #define X86_VENDOR_NUM 9
75 #define X86_VENDOR_UNKNOWN 0xff
78 * capabilities of CPUs
81 extern struct cpuinfo_x86 boot_cpu_data;
82 extern struct cpuinfo_x86 new_cpu_data;
83 extern struct tss_struct doublefault_tss;
86 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
87 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
88 #define current_cpu_data cpu_data(smp_processor_id())
90 #define cpu_data(cpu) boot_cpu_data
91 #define current_cpu_data boot_cpu_data
95 * the following now lives in the per cpu area:
96 * extern int cpu_llc_id[NR_CPUS];
98 DECLARE_PER_CPU(u8, cpu_llc_id);
99 extern char ignore_fpu_irq;
101 void __init cpu_detect(struct cpuinfo_x86 *c);
103 extern void identify_boot_cpu(void);
104 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
107 extern void detect_ht(struct cpuinfo_x86 *c);
109 static inline void detect_ht(struct cpuinfo_x86 *c) {}
112 /* from system description table in BIOS. Mostly for MCA use, but
113 others may find it useful. */
114 extern unsigned int machine_id;
115 extern unsigned int machine_submodel_id;
116 extern unsigned int BIOS_revision;
117 extern unsigned int mca_pentium_flag;
120 * User space process size: 3GB (default).
122 #define TASK_SIZE (PAGE_OFFSET)
125 struct i387_fsave_struct {
133 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
134 long status; /* software status information */
137 struct i387_fxsave_struct {
148 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
149 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
151 } __attribute__ ((aligned (16)));
153 struct i387_soft_struct {
161 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
162 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
164 unsigned long entry_eip;
168 struct i387_fsave_struct fsave;
169 struct i387_fxsave_struct fxsave;
170 struct i387_soft_struct soft;
177 #define ARCH_MIN_TASKALIGN 16
179 struct thread_struct {
180 /* cached TLS descriptors. */
181 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
183 unsigned long sysenter_cs;
188 /* Hardware debugging registers */
189 unsigned long debugreg0;
190 unsigned long debugreg1;
191 unsigned long debugreg2;
192 unsigned long debugreg3;
193 unsigned long debugreg6;
194 unsigned long debugreg7;
196 unsigned long cr2, trap_no, error_code;
197 /* floating point info */
198 union i387_union i387;
199 /* virtual 86 mode info */
200 struct vm86_struct __user * vm86_info;
201 unsigned long screen_bitmap;
202 unsigned long v86flags, v86mask, saved_sp0;
203 unsigned int saved_fs, saved_gs;
205 unsigned long *io_bitmap_ptr;
207 /* max allowed port in the bitmap, in bytes: */
208 unsigned long io_bitmap_max;
209 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
210 unsigned long debugctlmsr;
211 /* Debug Store - if not 0 points to a DS Save Area configuration;
212 * goes into MSR_IA32_DS_AREA */
213 unsigned long ds_area_msr;
216 #define INIT_THREAD { \
217 .sp0 = sizeof(init_stack) + (long)&init_stack, \
219 .sysenter_cs = __KERNEL_CS, \
220 .io_bitmap_ptr = NULL, \
221 .fs = __KERNEL_PERCPU, \
225 * Note that the .io_bitmap member must be extra-big. This is because
226 * the CPU will access an additional byte beyond the end of the IO
227 * permission bitmap. The extra byte must be all 1 bits, and must
228 * be within the limit.
232 .sp0 = sizeof(init_stack) + (long)&init_stack, \
233 .ss0 = __KERNEL_DS, \
234 .ss1 = __KERNEL_CS, \
235 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
237 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
240 #define start_thread(regs, new_eip, new_esp) do { \
241 __asm__("movl %0,%%gs": :"r" (0)); \
244 regs->ds = __USER_DS; \
245 regs->es = __USER_DS; \
246 regs->ss = __USER_DS; \
247 regs->cs = __USER_CS; \
248 regs->ip = new_eip; \
249 regs->sp = new_esp; \
253 extern unsigned long thread_saved_pc(struct task_struct *tsk);
255 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
256 #define KSTK_TOP(info) \
258 unsigned long *__ptr = (unsigned long *)(info); \
259 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
263 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
264 * This is necessary to guarantee that the entire "struct pt_regs"
265 * is accessable even if the CPU haven't stored the SS/ESP registers
266 * on the stack (interrupt gate does not save these registers
267 * when switching to the same priv ring).
268 * Therefore beware: accessing the ss/esp fields of the
269 * "struct pt_regs" is possible, but they may contain the
270 * completely wrong values.
272 #define task_pt_regs(task) \
274 struct pt_regs *__regs__; \
275 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
279 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
281 static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
283 tss->x86_tss.sp0 = thread->sp0;
284 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
285 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
286 tss->x86_tss.ss1 = thread->sysenter_cs;
287 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
291 #ifdef CONFIG_PARAVIRT
292 #include <asm/paravirt.h>
295 static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
297 native_load_sp0(tss, thread);
299 #endif /* CONFIG_PARAVIRT */
301 /* generic versions from gas */
302 #define GENERIC_NOP1 ".byte 0x90\n"
303 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
304 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
305 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
306 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
307 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
308 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
309 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
312 #define K8_NOP1 GENERIC_NOP1
313 #define K8_NOP2 ".byte 0x66,0x90\n"
314 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
315 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
316 #define K8_NOP5 K8_NOP3 K8_NOP2
317 #define K8_NOP6 K8_NOP3 K8_NOP3
318 #define K8_NOP7 K8_NOP4 K8_NOP3
319 #define K8_NOP8 K8_NOP4 K8_NOP4
322 /* uses eax dependencies (arbitary choice) */
323 #define K7_NOP1 GENERIC_NOP1
324 #define K7_NOP2 ".byte 0x8b,0xc0\n"
325 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
326 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
327 #define K7_NOP5 K7_NOP4 ASM_NOP1
328 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
329 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
330 #define K7_NOP8 K7_NOP7 ASM_NOP1
333 /* uses eax dependencies (Intel-recommended choice) */
334 #define P6_NOP1 GENERIC_NOP1
335 #define P6_NOP2 ".byte 0x66,0x90\n"
336 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
337 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
338 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
339 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
340 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
341 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
344 #define ASM_NOP1 K8_NOP1
345 #define ASM_NOP2 K8_NOP2
346 #define ASM_NOP3 K8_NOP3
347 #define ASM_NOP4 K8_NOP4
348 #define ASM_NOP5 K8_NOP5
349 #define ASM_NOP6 K8_NOP6
350 #define ASM_NOP7 K8_NOP7
351 #define ASM_NOP8 K8_NOP8
352 #elif defined(CONFIG_MK7)
353 #define ASM_NOP1 K7_NOP1
354 #define ASM_NOP2 K7_NOP2
355 #define ASM_NOP3 K7_NOP3
356 #define ASM_NOP4 K7_NOP4
357 #define ASM_NOP5 K7_NOP5
358 #define ASM_NOP6 K7_NOP6
359 #define ASM_NOP7 K7_NOP7
360 #define ASM_NOP8 K7_NOP8
361 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
362 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
363 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
364 #define ASM_NOP1 P6_NOP1
365 #define ASM_NOP2 P6_NOP2
366 #define ASM_NOP3 P6_NOP3
367 #define ASM_NOP4 P6_NOP4
368 #define ASM_NOP5 P6_NOP5
369 #define ASM_NOP6 P6_NOP6
370 #define ASM_NOP7 P6_NOP7
371 #define ASM_NOP8 P6_NOP8
373 #define ASM_NOP1 GENERIC_NOP1
374 #define ASM_NOP2 GENERIC_NOP2
375 #define ASM_NOP3 GENERIC_NOP3
376 #define ASM_NOP4 GENERIC_NOP4
377 #define ASM_NOP5 GENERIC_NOP5
378 #define ASM_NOP6 GENERIC_NOP6
379 #define ASM_NOP7 GENERIC_NOP7
380 #define ASM_NOP8 GENERIC_NOP8
383 #define ASM_NOP_MAX 8
385 /* Prefetch instructions for Pentium III and AMD Athlon */
386 /* It's not worth to care about 3dnow! prefetches for the K6
387 because they are microcoded there and very slow.
388 However we don't do prefetches for pre XP Athlons currently
389 That should be fixed. */
390 static inline void prefetch(const void *x)
392 alternative_input(ASM_NOP4,
398 #define ARCH_HAS_PREFETCH
400 /* 3dnow! prefetch to get an exclusive cache line. Useful for
401 spinlocks to avoid one state transition in the cache coherency protocol. */
402 static inline void prefetchw(const void *x)
404 alternative_input(ASM_NOP4,
410 extern void enable_sep_cpu(void);
411 extern int sysenter_setup(void);
413 /* Defined in head.S */
414 extern struct desc_ptr early_gdt_descr;
416 extern void cpu_set_gdt(int);
417 extern void switch_to_new_gdt(void);
418 extern void cpu_init(void);
419 extern void init_gdt(int cpu);
421 #endif /* __ASM_I386_PROCESSOR_H */